SoC Hardware Overview: Interconnect and Memory (OEMB5500INT)

Course Description

In this training you will learn about the Hard Processor Subsystem (HPS) in the Cyclone® V, Arria® V, and Arria 10 SoC device. We will discuss the AMBA® AXI™ bridges, the Level 3 and Level 4 interconnects, and various types of memory that are included in the HPS.

At Course Completion

You will be able to:

• Understand the AMBA AXI bridge architecture
• Understand the Level 3 and Level 4 interconnect
• Understand the On-Chip RAM and Boot ROM
• Understand the features of the HPS SDRAM

Skills Required

• Basic knowledge of FPGA architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals

Related Courses

Below are the related courses you may be interested in:

• SoC Hardware Overview: the Microprocessor Unit
• Software Design Flow for an Arm*-based Intel® SoC FPGA

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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