Design Evaluation for Timing Closure (ODSWTC02)
Course Description
This training will teach you what to do when you have timing failures in your design, when your timing reports are red. You will learn how to review and evaluate compilation results in the Intel® Quartus® Prime Pro software v. 18.1 to identify problems that make the design fail timing. You will learn how to fix some of the problems.At Course Completion
You will be able to:
- Review compilation results to identify problems
- Check details of specific failing paths
- Make changes to software settings or the RTL to close timing
Skills Required
- An understanding of basic FPGA design flow
- A solid working knowledge of the Quartus II software
- Familiarity with the TimeQuest timing analyzer
- Familiarity with Chip Planner
Prerequisites
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
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Location | Dates | Price | Registration |
---|---|---|---|
On-line | Anytime | Free | Register Now |