Course DescriptionThis course presents some considerations when crossing clock domains in Intel® FPGAs. The course reviews metastability and synchronizer circuits, goes over the CDC Viewer reporting tool found in Intel Quartus® Pro Software Timing Analyzer, and uses a simple design to cross clock domains.
At Course Completion
You will be able to:
- Use the CDC Viewer in Timing Analyzer
- Analyze clock domain crossing designs
- Constrain clock domain crossing designs
- Familiarity with Intel Quartus Prime Pro software
- Familiarity with Timing Analyzer