Clock Domain Crossing Considerations (ODSWCDCC)

Course Description

This course presents some considerations when crossing clock domains in Intel® FPGAs. The course reviews metastability and synchronizer circuits, goes over the CDC Viewer reporting tool found in Intel Quartus® Pro Software Timing Analyzer, and uses a simple design to cross clock domains.

At Course Completion

You will be able to:

• Use the CDC Viewer in Timing Analyzer
• Analyze clock domain crossing designs
• Constrain clock domain crossing designs

Skills Required

• Familiarity with Intel Quartus Prime Pro software
• Familiarity with Timing Analyzer

Prerequisites

We recommend completing the following courses:

• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Timing Analyzer: Intel® Quartus® Prime Software Integration & Reporting
• Timing Analyzer: Introduction to Timing Analysis
• Timing Analyzer: Timing Analyzer GUI
• Using the Intel® Quartus® Prime Standard Edition Software: An Introduction

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Dynamic Reconfiguration in Altera Transceiver Devices (Legacy Course)
• Transceiver Reconfiguration in Altera 28-nm Devices (Legacy Course)

Related Courses

Below are the related courses you may be interested in:

• Managing Metastability with the Quartus II Software (Legacy Course)

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 300

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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