Become an FPGA Designer in 4 Hours (ODSWBECOME)
Course Description
This course gives you basic skills to design with Intel FPGAs. It uses lecture, demonstrations & labs that can be completed in 4 hours. Learn architectural features of Intel FPGAs & how the Intel Quartus® Prime software works. The labs train you to:
1) Set up a design project, 2) set assignments & compile a design, 3) perform timing analysis, 4) perform power analysis, 5) download a design to hardware, 6) debug a design with the Signal Tap logic analyzerThe course is most beneficial using the Cyclone® V GX Starter Kit or the MAX 10 DE10-Lite Kit from Terasic. Consult Terasic/ Digikey websites for details on the kits. If you choose not to purchase a kit, you can complete all labs except Design Download & Debug. Links to download lab files are in the Notes section.
At Course Completion
You will be able to:
- Describe the features that make up modern FPGA devices
- Use many of the common features of the Quartus Prime design software including IP Generation, I/O Assignments, Compilation, Timing Analysis, Power Analysis, Design Download and Design Debug
- Understand how to generate timing constraints for synchronous and asynchronous based systems
- Download a completed design from your PC to a development kit
- Use the SignalTap II Logic Analyzer to debug your design
Skills Required
- Basic understanding of digital logic design
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: