University Self-Guided Lab: Become an FPGA Designer in 4 Hours (ODSWBECOME)

Course Description

This course gives you basic skills to design with Intel® FPGAs in 4 hour using a mixture of lecture, demonstrations & labs. Learn architectural features of Intel FPGAs & how the Intel Quartus® Prime software works. The labs train you to:

1. Set up a design project
2. Set assignments & compile a design
3. Perform timing analysis
4. Perform power analysis
5. Download a design to hardware
6. Debug with the Signal Tap logic analyzer

The course is most beneficial using the Cyclone® V GX Starter Kit or the DE10-Lite Kit from Terasic. Consult Terasic/ Digikey websites for details on the kits. If you choose not to purchase a kit, you can complete all labs except Design Download & Debug. Links to download lab files are in the Notes section.

At Course Completion

You will be able to:

• Describe the features that make up modern FPGA devices
• Use many of the common features of the Intel Quartus Prime software including IP Generation, I/O Assignments, Compilation, Timing Analysis, Power Analysis, Design Download and Design Debug
• Understand how to generate timing constraints for synchronous and asynchronous based systems
• Download a completed design from your PC to a development kit
• Use the Signal Tap embedded Logic Analyzer to debug your design

Skills Required

• Basic understanding of digital logic design

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Custom IP Development Using Avalon® and Arm* AMBA* AXI Interfaces
• Introduction to Platform Designer
• Using the Nios II Processor: Custom Components and Instructions

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 200

Class Schedule

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