Signal Tap Logic Analyzer: Basic Configuration & Trigger Conditions (ODSW1171)

22 Minutes Online Course

Course Description

This training is part 2 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This part of the training walks through many of the Signal Tap options found in the Signal Configuration section of the tool, including the selection of a sampling clock, choosing buffer options, and the many ways of performing storage qualification. It also goes into detail on how to create basic trigger conditions.

At Course Completion

You will be able to:

  • Set up basic trigger conditions including Basic AND, Basic OR, and comparison triggers
  • Choose Signal Configuration options such as buffer type and configuration, pipelining, and storage qualification

Skills Required

  • Basic knowledge of the Intel® Quartus® Prime Software
  • Knowledge of external logic analyzer operations (optional)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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