Using the Quartus II Software: Chip Planner (Legacy Course) (ODSW1155)

60 Minutes Online Course

Course Description

This training will introduce you to the Quartus® II software version 12.0 Chip Planner. You will learn how to analyze your design using the Chip Planner features such as floorplan views, critical path analysis and routing congestion analysis. Next you will learn how to create and control LogicLock™ regions using the Chip Planner. Finally, you will learn to use the Chip Planner along with other Quartus II integrated tools to perform Engineering Change Orders.

At Course Completion

You will be able to:

  • Perform design analysis with Chip Planner
  • Work with location assignments & LogicLock regions
  • Perform Engineering Change Orders (ECOs) in Chip Planner along with Quartus II integrated tools such as the Resource Property Editor and Change Manager

Skills Required

  • Completion of “Using the Quartus II Software: An Introduction” OR
  • Understanding or knowledge of:
  • Quartus II software and Altera devices
  • Quartus II Engineering Change Order (ECO) flow
  • Location assignments & LogicLock methodology with Timing Closure Floorplan


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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