Introduction to Incremental Compilation in the Intel® Quartus® Prime Standard Edition Software (ODSW1136)
Course Description
You will learn how to preserve design performance and reduce compilation time by using the incremental compilation feature of the Quartus® II software, now known as the Intel® Quartus Prime Standard Edition software. By the end of this training, you will be able to use LogicLock™ regions to physically partition (floorplan) your design. You will be able to decide when and when not to use incremental compilation, how best to set up your design hierarchy and source code to support incremental compilation, and how to segment your design into logical design partitions. You will also be able to apply the incremental compilation methodology to both the top-down and team-based design flows.At Course Completion
You will be able to:
- Create & manage LogicLock regions to physically partition a design
- Create & manage good design partitions
- Determine whether your next design can benefit from incremental compilation
- Set up & perform incremental compilation
- Use incremental compilation in the top-down & team-based design flows
- Set up a top-level project framework with constraints for a team-based design flow
- Generate design partition scripts
- Export a lower-level design & import it into the top-level design
Skills Required
- Background in digital logic design
- Familiarity with using the Quartus II software
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Related Courses
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
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| Location | Dates | Price | Registration |
|---|---|---|---|
| On-line | Anytime | Free | Register Now |