Simulating Designs with 3rd Party EDA Simulators (Legacy Course) (ODSW1122)

35 Minutes Online Course

Course Description

This training will teach you about the RTL and gate level simulation flows for FPGA designs. You will learn which EDA simulators are supported. You will learn how to generate IPFS (intellectual property functional simulation) models, EDA netlists, and how to convert a BDF (block design file) to a HDL (hardware description language) file. You will also learn how to set up libraries to perform manual RTL or gate level simulations. This training will focus on guiding you to use NativeLink and EDA Simulation Library Compiler in the Quartus® II software v. 9.1 to facilitate the transfer of information between the Quartus II software and EDA tools. Finally, you will learn how to create a Verilog HDL test bench.

At Course Completion

You will be able to:

  • Understand the Altera design flow
  • Understand 3rd party EDA simulation flow
  • Pick a 3rd party EDA simulator
  • Generate IPFS models
  • Convert a BDF to HDL
  • Use the EDA Simulation Library Compiler
  • Set up a manual RTL simulation in 3rd party simulator
  • Generate EDA netlist
  • Set up a manual gate level simulation in 3rd party simulator
  • Use NativeLink
  • Create a test bench in Verilog HDL

Skills Required

  • Background in digital logic design

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

Class Schedule

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