This training is part 2 of 4. Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. The Timing Analyzer, part of the Intel® Quartus® Prime software, is an easy-to-use tool for creating Synopsys* design constraints (SDC) files and for generating detailed timing reports to shorten the process of timing closure. This part of the training introduces you to the Timing Analyzer graphical user interface and the basics of using the tool to create SDC files and generate timing reports.
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At Course Completion
You will be able to:
- Understand the features of the Timing Analyzer graphical user interface
- Perform the steps required for using the tool, including the creation of a timing netlist
- Select and switch between timing models available for the targeted device
- Background in digital logic design
- An understanding of basic FPGA design flow
- A solid working knowledge of the Intel Quartus Prime software
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: