Implementing Video Systems (Legacy Course) (ODSP1118)

70 Minutes Online Course

Course Description

This training introduces Altera’s video platform & design flow. It will highlight various design considerations & debugging techniques. You will understand the algorithmic constraints of video & image processing IP. You will learn to decode Avalon streaming video data & control packets. You will learn how to run-time configure your video & image processing algorithms. You will be able to accurately estimate the external memory bandwidth requirements & implement efficient memory architecture for your system. Furthermore, you will see how the clocked videos are translated to/from Avalon ST video packets & how genlock & framelock can be achieved with Altera’s video solution. Finally, you will learn how to best debug your video system & to extend the capabilities of existing design examples.

At Course Completion

You will be able to:

  • Describe the Altera video design framework
  • Describe the general design flow of video system
  • Decode Altera Video streaming data and control packets
  • Run-time configure the video and image processing Megacore® IPs
  • Understand various algorithmic constraints
  • Understand external memory considerations and implement efficient external memory architectures
  • Understand clocking considerations
  • Understand when to use frame buffers
  • Describe general debugging strategies

Skills Required

  • Basic knowledge of the Quartus II software
  • Background in DSP design
  • Understanding or knowledge of setting up external memory interfaces
  • Working knowledge of designing with Nios II processor and SOPC Builder
  • Familiarity with Altera’s Video and Image Processing Suite

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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