Using Design Space Explorer (ODSE)

21 Minutes Online Course

Course Description

Learn how to use the Quartus® II Design Space Explorer (DSE) as an aid to remote and parallel compilation. The training starts with a background about the challenges of larger FPGA devices and how DSE can help you face this challenge. Then you will learn the steps to use DSE to explore a design and optimize it for timing, area or power. You will see an example that demonstrates the DSE features. Finally, you will learn about how to use DSE via the command line. This training was developed for the Quartus II software version 15.0.

At Course Completion

You will be able to:

  • Understand the issues with large FPGA designs
  • Explore your design using DSE features such as: Remote or parallel compilation, Seed sweep, and Optimize for timing, area or power
  • Use DSE via the command line

Skills Required

  • Background in digital logic design
  • An understanding of basic FPGA design flow
  • Basic understanding of the Quartus II user interface

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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