Constraining Double Data Rate Source Synchronous Interfaces (ODDR1000)

29 Minutes Online Course

Course Description

This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock constraints, data constraints, and timing exceptions for both input and output DDR interfaces. Finally, you’ll learn how to analyze DDR source synchronous interface timing with the TimeQuest timing analyzer. This course uses the Quartus® II software v13.0.

At Course Completion

You will be able to:

  • Constrain double data rate source synchronous interfaces with SDC constraints
  • Analyze timing for double data rate source synchronous interfaces with the TimeQuest timing analyzer

Skills Required

  • Knowledge of static timing analysis concepts
  • Knowledge of source synchronous interface theory
  • Completion of “Constraining Source Synchronous Interfaces” online training

Prerequisites

We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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