Constraining Source Synchronous Interfaces (OCSS1000)
Course Description
This training will show you how to constrain and analyze single data rate source synchronous interfaces with the TimeQuest timing analyzer in the Quartus® II software. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write SDC constraints to constrain single data rate source synchronous inputs and outputs. You will also learn to use the TimeQuest timing analyzer to report and analyze timing for source synchronous inputs and outputs. This course uses the Quartus II software v13.0.At Course Completion
You will be able to:
- Describe basic functionality of a source synchronous interface
- Constrain single data rate source synchronous interfaces with SDC constraints
- Analyze timing for single data rate source synchronous interfaces with the TimeQuest timing analyzer
Skills Required
- Completion of “TimeQuest Timing Analyzer” online training OR
- Understanding or knowledge of:
- Static timing analysis concepts
- How to create SDC constraints for clocks and IOs
- TimeQuest timing analyzer reporting features
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: