This training will show you how to constrain and analyze single data rate source synchronous interfaces with the Timing Analyzer in the Intel® Quartus® Prime software. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write Synopsys* Design Constraints (SDC) to constrain single data rate source synchronous inputs and outputs. You will also learn to use the Timing Analyzer to report and analyze timing for source synchronous inputs and outputs.
*Other names and brands may be claimed as the property of others.
At Course Completion
You will be able to:
- Describe basic functionality of a source synchronous interface
- Constrain single data rate source synchronous interfaces with SDC constraints
- Analyze timing for single data rate source synchronous interfaces with the Timing Analyzer
- Completion of Timing Analyzer online courses
- OR working knowledge of Static timing analysis concepts, creating SDC constraints for clocks and I/Os and Timing Analyzer reporting features
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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