消除Hyper-Retiming中的障碍 (Chinese Version of Eliminating Barriers to Hyper-Retiming) (OCS10EHYPRET)

30 Minutes Online Course

Course Description

通过对消除Hyper-Retiming障碍的学习,你将进一步加深对Hyper-Retiming的认识。你将学习到在Quartus® II 设计流程中哪些因素会阻碍Hyper-Retimer模块运用Stratix® 10 Hyper-Registers对设计性能的改善。同时你将学习到多种修改设计的手段,用以克服Hyper-Retiming过程中的障碍。

At Course Completion

You will be able to:

  • 描述阻碍Hyper-Retiming 优化的设计结构
  • 对RTL进行修改以消除Hyper-Retiming过程中的限制

Skills Required

  • 熟悉FPGA/CPLD设计流程
  • 熟悉Quartus® II 设计软件
  • 熟悉Verilog 或者 VHDL 编写的可综合结构

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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