VHDL基础 (Chinese Version of VHDL Basics) (OCHDL1110)

48 Minutes Online Course

Course Description


At Course Completion

You will be able to:

  • 理解仿真环境与综合环境的区别
  • 使用VHDL设计单元,包括实体、结构体、配置以及封装
  • 使用语言构念,例如赋值语句、进程语句、条件语句、选择语句以及循环语句建立VHDL模型
  • 创建可综合模型(行为化的编码风格)
  • 使用VHDL组件例化来创建分层(结构化编码风格)

Skills Required

  • 数字逻辑设计背景
  • 推荐事先了解一门编程语言(如:C语言)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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