约束双倍数据速率源同步接口 (Chinese Version of Constraining Double Data Rate Source Synchronous Interfaces) (OCDDR1000)

29 Minutes Online Course

Course Description

此次培训介绍双倍数据速率接口,以及对其进行约束所涉及到的一些难题。您将学习输入和输出DDR接口的时钟约束、数据约束和时序例外。最后,您将学习怎样采用TimeQuest时序分析器分析DDR源同步接口的时序。这一课程使用了Quartus® II软件v13.0。

At Course Completion

You will be able to:

  • 采用SDC约束功能来约束双倍数据速率源同步接口
  • 采用TimeQuest时序分析器分析双倍数据速率源同步接口的时序

Skills Required

  • 掌握静态时序分析概念
  • 源同步接口理论知识
  • 完成“约束源同步接口”在线培训

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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