Avalon Verification Suite (OAVL1100)

24 Minutes Online Course

Course Description

An Avalon interface refers to the connection between intellectual property (IP) cores used in Altera FPGAs. This connection is compliant with the Avalon Interface Specification. The Avalon Verification Suite is a collection of Altera verification IP cores which facilitate the verification process of your own IP core. In this training, you will learn about the Altera Avalon Verification Suite and the support by various simulators. Next, you will learn about the Avalon Verification Suite Application Programming Interface (API) and parameters. You will see some design examples to help you get started quickly. This training is based on the Quartus® II software v. 12.0.

At Course Completion

You will be able to:

  • Use the Avalon Bus Functional Model for IP verification
  • Use the Avalon Monitor for test assertion and coverage

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Quartus II design software including Qsys

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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