Advanced System Design Using Platform Designer: Component & System Simulation (OAQSYSSIM)

28 Minutes Online Course

Course Description

This training is part 1 of 4. The Platform Designer system integration tool saves significant time by automatically generating interconnect logic to connect IP functions and subsystems. In this training you will learn about some advanced capabilities of the tool. In this first part, you will learn how to verify an individual component or an entire system design through simulation. You'll learn about the verification IP included in the software in the form of Bus Functional Models (BFMs), essentially golden reference components for the supported standard interfaces, and monitors. You'll see how Platform Designer makes it easy to build a testbench system and how to use a simple API in your testbench code to control the operation of the BFMs in the system during a simulation.

At Course Completion

You will be able to:

  • Know about the Verification IP Suite included with the Intel Quartus Prime software
  • Understand how to use Platform Designer to generate testbench systems
  • Write testbench code using the Bus Functional Model (BFM) API to control BFMs during a simulation

Skills Required

  • Background in digital logic design
  • Familiarity with the Intel Quartus Prime software
  • Familiarity with the Platform Designer system design tool

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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