On-Chip Debugging of Memory Interfaces in Intel® Agilex™ Devices (OAGMEM104)

45 Minutes Online Course

Course Description

This training is part 4 of 4. Intel® Agilex devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 3.2 Gbps on some devices. This part of the training discusses the use of the EMIF Debug Toolkit and the new Traffic Generator 2.0. The Debug Toolkit provides runtime information through a JTAG connection or through software control on the calibration and available margin in a memory interface. The Traffic Generator lets you create and send custom data patterns to the memory for post-calibration tests. Due to the changes in implementation from previous devices, this training also discusses what is required to use these tools with designs that include multiple memory interfaces.

At Course Completion

You will be able to:

  • Perform on-chip debugging of a memory interface using the EMIF Debug Toolkit
  • Generate custom traffic patterns for testing using Traffic Generator 2.0
  • Configure a design with multiple memory interfaces to work with these tools

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with memory interfaces in Intel FPGA devices from the listed prerequisite training classes

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

Result Showing 1

LocationDatesPriceRegistration
On-lineAnytimeFreeRegister Now

Request a class in your region.