Verifying Memory Interfaces in Intel® Agilex™ Devices (OAGMEM103)

27 Minutes Online Course

Course Description

This training is part 3 of 4. Intel® Agilex™ devices introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR4 running at up to 3.2 Gbps on some devices. This part of the training discusses how to perform a simulation of the altera_emif_fm IP using a generated example design. When generated, the IP creates all the files needed to perform a simulation. Timing analysis of the IP is also discussed along with suggestions for timing closure. The hard resources used for altera_emif_fm along with easier-to-read timing reports simplify analysis and closure.

At Course Completion

You will be able to:

  • Verify the functionality of an Intel® Agilex FPGA EMIF design through simulation
  • Perform a timing analysis of both the core logic and I/O periphery for a memory interface
  • Understand steps to take in debugging an interface and possible solutions for problems

Skills Required

  • Background in digital logic design
  • Basic knowledge of memory interfaces
  • Familiarity with the Intel® Quartus® Prime software
  • Familiarity with memory interfaces in Intel FPGA devices from the listed prerequisite training classes

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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