Advanced Signal Conditioning for Arria® 10 FPGA Transceivers (OADVSIGA10)

32 Minutes Online Course

Course Description

In this training, you will learn about the signal conditioning features of the Arria® 10 FPGA. You will learn the causes of signal attenuation and noise that lead to decreased signal integrity. You will learn about the following blocks contained in the receive buffer: CTLE, DFE, and VGA. You will also learn about the VOD and pre-emphasis blocks in the transmit buffer. A flow for link tuning using Transceiver Toolkit will be presented.

At Course Completion

You will be able to:

  • Understand the causes of signal attenuation and noise in a channel
  • Describe the Arria® 10 FPGA transceiver features for signal conditioning
  • Set up a physical system for link tuning
  • Use Transceiver Toolkit to determine optimal analog transceiver settings

Skills Required

  • Familiarity with common high-speed transceiver architecture


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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