Application Development on the Acceleration Stack for Intel® Xeon® CPU with FPGAs (OACCELSW)

46 Minutes Online Course

Course Description

The Acceleration Stack for Intel Xeon CPU with FPGAs is a robust collection of software, firmware, and tools intended to make it easier to develop and deploy Intel FPGAs for workload optimization in the data center. In this training, we will discuss how to develop host code that can communicate with the FPGA accelerator using the Open Programmable Acceleration Engine (OPAE) as well as abstracting away the OPAE layer using OpenCL™. *OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos

At Course Completion

You will be able to:

  • Understand the contents of the Open Programmable Acceleration Engine
  • Get started writing host code that communicates with the OPAE layer to run acceleration workloads on an FPGA accelerator

Skills Required

  • Basic understanding of software programming and Linux operating systems

Prerequisites

We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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