Building RTL Workloads for the Acceleration Stack for Intel® Xeon® CPU with FPGAs (OACCELRTL)

37 Minutes Online Course

Course Description

The Acceleration Stack for Intel Xeon CPU with FPGAs is a robust collection of software, firmware, and tools intended to make it easier to develop and deploy Intel FPGAs for workload optimization in the data center. In this training, we will discuss how to develop an Accelerator Function Unit (AFU) for the FPGA using traditional RTL development and debug methods, and how to interact with it from the Acceleration Stack software using the Open Programmable Acceleration Engine (OPAE).

At Course Completion

You will be able to:

  • Know the basics of using RTL tools & methods to develop an accelerator function for the FPGA that interacts with the Acceleration Stack
  • Understand the Core Cache Interface (CCI-P) that connects the accelerator function to the FPGA Interface Manager and Intel Xeon CPU
  • Use the Open Programmable Acceleration Engine (OPAE) to interact with the accelerator function
  • Perform a simulation of your accelerator using the AFU Simulation Environment
  • Generate the AFU bitstream to configure the FPGA

Skills Required

  • Basic understanding of FPGAs


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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