Low-Density Parity-Check (LDPC) Codes Intel® FPGA IP for 5G Systems (O5GLDPC)


Course Description

As wireless vendors begin to deploy 5G-based technology, Low-Density Parity-Check (LDPC) codes are replacing turbo codes as the coding of choice for forward error correction. This training introduces the Intel® FPGA LDPC Codes IP cores, namely the encoder and decoder blocks . It shows the basics of how these blocks work and then describes how, when using the cores, you can verify correct operation in both the simulation and hardware environments using a core-generated reference design.

At Course Completion

You will be able to:

  • Understand the basic function of the 5G LDPC codes IP core
  • Verify the functionality of the 5G LDPC codes IP core in simulation
  • Verify the functionality of the 5G LDPC codes IP core in hardware using the Signal Tap logic analyzer

Skills Required

  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus Prime Pro design software
  • Knowledge of forward error correction algorithms, particularly low-density partity-check codes

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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