This course will instruct you in how to configure the PHY layer found in Cyclone® V, Arria® V and Stratix® V embedded transceivers for a custom protocol implementation. You will learn details regarding blocks found in high-speed transceivers as well as the various signals used to interact with those blocks to build high-speed serial interfaces. You will learn how to use the Quartus® II software version 13.0 to configure the transceivers to build a custom PHY and to generate design logic to hook up to your own higher layer functional blocks.
For Cyclone IV, Arria II, Stratix IV and HardCopy® IV devices, please see the online training High-Speed Serial Protocol Design with Altera Transceiver Devices.
At Course Completion
You will be able to:
- Describe the features of the Altera 28-nm transceivers
- Interface a custom serial protocol solution to embedded transceivers
- Use the Native PHY IP cores to configure a custom PCS and PHY solution
- Familiarity with common high-speed transceiver architecture OR completion of the online course Transceiver Basics
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus II design software
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Altera training curriculum: