Introduction to the 10Gb Ethernet PHY Intel® FPGA IP Cores (O10GPHY)

Course Description

This online course will instruct you in how to use Intel® FPGA solutions to build a 10Gb Ethernet design targeting Intel FPGA transceiver devices using the Intel Quartus® Prime software. In this course, you will learn how to use the XAUI, 10GBASE-R, 1G/10G, 10GBASE-KR and Multi-Rate PHY IP cores to implement the required PHY layer of your 10Gb Ethernet design.

At Course Completion

You will be able to:

• Describe the features and functionality of the following Ethernet PHY IP cores: XAUI, 10GBASE-R, 1G/10G, 10GBASE-KR and Multi-Rate

Skills Required

• Understanding of the 10Gb Ethernet technology specifications
• Familiarity with common high-speed transceiver architecture OR viewing the following course: Transceiver Basics
• Familiarity with FPGA/CPLD design flow
• Familiarity with the Intel Quartus Prime design software
• Some familiarity with Platform Designer

Prerequisites

We recommend completing the following courses:

• Intel® Stratix® 10 FPGA L- and H-Tile Transceiver Basics
• Transceiver Basics for 20 nm and 28 nm Devices

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Using the 10Gb Ethernet Design Examples

Related Courses

Below are the related courses you may be interested in:

• Introduction to the Low Latency 10Gb Ethernet MAC Intel® FPGA IP Core

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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