Using the 10Gb Ethernet Design Examples (O10GEX)

Course Description

This online course will instruct you in how to use Altera® solutions to build a 10Gb Ethernet design targeting Altera transceiver devices using the Quartus® Prime software In this course, you will learn how to use the 10Gb Ethernet Design Examples and the Qsys design tool to implement an entire 10Gb Ethernet solution.

At Course Completion

You will be able to:

• Locate or generate a 10Gb Ethernet design example
• Compile and simulate the example design
• Compile and test the example design in hardware

Skills Required

• Understanding of the 10Gb Ethernet technology specifications
• Familiarity with common high-speed transceiver architecture OR viewing the following course: "Transceiver Basics"
• Familiarity with FPGA/CPLD design flow
• Familiarity with the Quartus Prime design software
• Some familiarity with Qsys

Prerequisites

We recommend completing the following courses:

• Introduction to the Low Latency 10Gb Ethernet MAC Intel® FPGA IP Core
• Transceiver Basics for 20 nm and 28 nm Devices

Related Courses

Below are the related courses you may be interested in:

• Introduction to the 10Gb Ethernet PHY Intel® FPGA IP Cores

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

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Location	Dates	Price	Registration
On-line	Anytime	Free	Register Now

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