In this course, you will learn how you can build high-speed, gigabit interfaces using the 20-nm embedded transceivers found in Arria® 10 FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration interface that you can use dynamically adjust transceiver settings to add flexibility to your transceiver design. Lastly, you will learn how to create application and control logic that effectively manages Arria 10 transceiver resources.
At Course Completion
You will be able to:
- Implement high-speed serial protocols in Arria® 20-nm embedded transceivers
- Simulate transceiver operation using a generated simulation setup script file
- Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations
- Optimize analog settings to improve link behavior using Altera tools
- Employ transceiver reconfiguration to dynamically change transceiver behavior in-system
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Quartus Prime Pro design software
- Familiarity with FPGA architecture
- Familiarity with high-speed interfaces and transmission protocols is helpful, but not required
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.