Course DescriptionThis workshop builds on the tools and techniques learned in the Performance Optimization with Stratix® 10 Hyperflex Architecture and Advanced Optimization with Stratix 10 Hyperflex Architecture training courses. This workshop provides an environment where an FPGA designer can sharpen their optimization skills by exercising those techniques on provided design blocks, while proctored by an Intel FPGA instructor. Note: this class is 90% lab time with only 10% lecture.
At Course Completion
You will be able to:
- Use Fast Forward Compile reports to influence optimization decisions on designs targeting the Intel Hyperflex architecture
- Improve clocking speed by implementing Intel Hyperflex architecture design recommendations on FPGA logic
- Good HDL coding skills
- Familiarity with the Intel® Stratix® 10 FPGA Hyperflex™ architecture
- Completion of the "Performance Optimization with Intel Stratix 10 FPGA Hyperflex Architecture" and "Advanced Optimization with Intel Stratix 10 FPGA Hyperflex Architecture" instructor-led training courses or all equivalent online training courses (see curricula)
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.