In the Performance Optimization with Intel® Stratix® 10 FPGA Hyperflex™ Architecture course, you will learn Intel Quartus® Prime Pro software features and some basic design techniques that will enable your designs to take advantage of the Intel Stratix 10 FPGA Hyperflex architecture. In the training, you will learn two steps to improving your performance with the Intel Hyperflex architecture, namely Hyper-Retiming and Hyper-Pipelining, with each step allowing you to move your design up the performance curve.
Note: While the focus of this course is the Intel Stratix 10 device family, many of the techniques you will learn can be used to improve performance in other device architectures.
At Course Completion
You will be able to:
- Describe the Intel Stratix 10 device architecture
- Enable the Intel Quartus Prime Pro software features that take advantage of the Intel Hyperflex architecture
- Evaluate possible design improvements using the Intel Quartus Prime Pro software’s Fast Forward Compile feature
- Improve your Intel Stratix 10 FPGA design performance by understanding and enabling Hyper-Retiming
- Improve your Intel Stratix 10 FPGA design performance by implementing zero-latency Hyper-Pipelining
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro design software
- Familiarity with Verilog or VHDL synthesizable design structures
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.