Are you targeting an Intel® Stratix® 10 device & want to learn how your design can reach maximum core performance?
In this course, you will learn design techniques to unleash the full potential of the Intel Stratix 10 FPGA Hyperflex architecture using Hyper-Optimization. Learn how to use the Intel Quartus® Prime Pro Edition software to identify logic structures limiting retiming and thus design performance. Learn to modify your coding style & logic structures &, as a result, allow your design to achieve clock rates of up to 2 times when compared to a non-optimized design, without changing overall design functionality.
Note: While the focus of this course is the Intel Stratix 10 device family, many techniques can be used to improve performance in other FPGA devices.
At Course Completion
You will be able to:
- Learn to interpret complex retiming reports to locate & understand critical chains, design paths requiring further optimization for improved performance
- Learn Hyper-Optimization techniques to restructure design logic to take advantage of the Intel Stratix 10 Hyperflex architecture (or any FPGA architecture) using techniques such as 1) Unrolling loops, 2) Pre-computation to reduce loop size, 3) Shannon’s Decomposition, 4) Time-domain multiplexing retiming, 5) Hyper-Folding, 6) Loop pipelining
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro Edition design software
- Familiarity with Verilog or VHDL synthesizable design structures
- Completion of the “Performance Optimization with Intel Stratix 10 FPGA Hyperflex Architecture” course
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
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