Are you targeting an Intel® Agilex™ or Intel Stratix® 10 device and wanting to learn how your design can reach the maximum core performance?
In this course, you will learn design techniques to unleash the full potential of the Intel Hyperflex™ architecture using Hyper-Optimization. You will begin by learning how to use the Intel Quartus® Prime Pro Edition software to identify logic structures that limit retiming and design performance. Afterwards, you will see how you can replace those structures with faster implementations, without changing design functionality.
Note: While the focus of this course is the Intel Hyperflex architecture, many techniques described can be used to improve performance in other Intel FPGA devices.
At Course Completion
You will be able to:
- Interpret reports to locate & understand critical chains, design paths that limit performance
- Use Hyper-Optimization techniques to restructure design logic to take advantage of the Intel Hyperflex architecture (or any FPGA architecture) using techniques such as
- Unrolling loops
- Pre-computation to reduce loop size
- Shannon’s Decomposition
- Time-domain multiplexing retiming
- Loop pipelining
- Familiarity with FPGA/CPLD design flow
- Familiarity with the Intel Quartus Prime Pro Edition design software
- Familiarity with Verilog or VHDL synthesizable design structures
- Completion of the “Performance Optimization with Intel Hyperflex Architecture” course or equivalent online course materials
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: