This course covers optimization techniques to implement high performance OpenCL™ applications on FPGAs. We'll use various debug & analysis tools available in the Intel® FPGA SDK for OpenCL™ software technology to boost performance of OpenCL kernels. The first half of the course focuses on the optimization of single work-item kernels & the utilization of channel constructs & OpenCL kernel pipes. The second half of the course focuses on the optimization of NDRange kernels & the effective utilization of FPGA memory resources. Throughout the course we will discuss good coding practices for FPGAs & tool features to improve OpenCL kernel performance on FPGAs.
*OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of Khronos.
At Course Completion
You will be able to:
- Use debugging & optimization tools
- Execute multiple OpenCL kernels in a task parallel fashion
- Boost performance of single work-item kernels
- Use single work-item kernels to implement parallel programming algorithms
- Use channels or OpenCL kernel pipes to increase communication performance
- Boost performance of NDRange kernels
- Improve usage of memory architectures
- Improve host-device communication efficiency
- Use good coding practices
- Boost data processing efficiency
- Attendance of the Introduction to OpenCL Programs for Intel FPGAs
- OR a good understanding of the OpenCL standard
We recommend completing the following courses:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.