You will learn & practice efficient coding techniques for writing synthesizable VHDL for Intel® FPGAs and CPLDs. While the course focuses on the Intel Quartus® Prime software, many concepts can be used with other synthesis tools. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to parameterize your Verilog design, increasing flexibility and reusability. You will be introduced to testbenches and the constructs used when building them. The exercises will use the Intel Quartus Prime software for synthesis & ModelSim* for Intel FPGA Edition Software for simulation.
*Other names and brands may be claimed as the property of others.
At Course Completion
You will be able to:
- Develop coding styles for efficient synthesis when:
- Targeting device features
- Inferring logic functions
- Using arithmetic operators
- Writing state machines
- Use Intel Quartus Prime software RTL Viewer to verify correct synthesis results
- Incorporate FPGA structural blocks in VHDL designs
- Write simple testbenches for verification
- Create parameterized designs
- Completion of the "Introduction to VHDL" course or some prior knowledge and use of VHDL
- Background in digital logic design
- Understanding of synthesis and simulation processes
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.