Advanced Verilog HDL Design Techniques (IHDL230)
Course Description
You will learn efficient coding techniques for writing synthesizable Verilog for Intel® FPGAs and CPLDs. While the course focuses on the Intel Quartus® Prime software, many concepts can be used with other synthesis tools. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to parameterize your Verilog design, increasing flexibility and reusability. You will be introduced to testbenches and the constructs used when building them. The exercises will use the Intel Quartus Prime software for synthesis and the ModelSim* for Intel® FPGA Edition software for simulation.
*Other names and brands may be claimed as the property of others.
At Course Completion
You will be able to:
- Implement synthesizable sequential and combinatorial RTL code
- Design finite state machines using multiple encoding schemes
- Develop simple testbenches for verification
- Use tools in the Intel Quartus Prime software to synthesize code and verify results
- Run functional simulations in the ModelSim for Intel FPGA Edition software
Skills Required
- Completion of the "Introduction to Verilog HDL" course or some prior knowledge and use of Verilog hardware description language (HDL)
- Background in digital logic design
- Understanding of synthesis and simulation processes
Prerequisites
We recommend completing the following courses:
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Related Courses
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
Class Schedule
No class is being offered at this time.