Course DescriptionOne of the greatest and most frustrating FPGA design challenges is closing timing. It is very common to find, after performing a complete timing analysis on an FPGA design, that one or more timing reports indicate a timing failure. How can this be corrected? The answer is not always obvious.
This class teaches the techniques used by design specialists to close timing on designs that “push the envelope” of performance. Example techniques include thoroughly analyzing the design for common timing failures, adjusting settings and assignments according to tool recommendations, selecting the correct clock resources, and adjusting HDL code for optimal performance.
At Course Completion
You will be able to:
- Employ best practices for closing timing on an FPGA design in the Intel Quartus Prime Pro software
- Analyze timing reports generated by Timing Analyzer as a starting point for timing closure
- Use the tools available in Intel Quartus Prime Pro software to help in meeting timing
- Choose settings/assignments to get the best performance
- Identify the most common types of timing failures and how to solve them
- Experience with PCs and the Windows operating system
- Completion of The Intel Quartus Prime Pro Software Design Series: Foundation course OR a working knowledge of the Intel Quartus Prime Pro software
- Completion of “Intel Quartus Prime Pro Software Design Series: Timing Analysis with Timing Analyzer” course OR a working knowledge of Synopsys Design Constraints (SDC) and Timing Analyzer
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.