Intel Quartus Prime Software Debug Tools (IDSW135)

Course Description

As FPGA designs become more complex, a larger part of development time is spent verifying designs. This course introduces the various debug tools included in the Intel® Quartus® Prime software & shows effective ways to debug an FPGA design using them, decreasing overall design development time.

The class discusses the Signal Tap embedded logic analyzer, Signal Probe, In-System Sources & Probes, the Logic Analyzer Interface, System Console, and others. The class mostly focuses on Signal Tap, including hands-on lab exercises utilizing the tool in a real design.

At Course Completion

You will be able to:

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Choose the appropriate debug tool to use for your design and situation

• Create trigger conditions and capture internal signal node levels during runtime with the SignalTap embedded logic analyzer
• Quickly route internal nodes to unused I/O pins using Signal Probe
• View & edit embedded memory contents using the In-System Memory Content Editor

Skills Required

• Completion of "The Quartus Software Design Series: Foundation" course OR a working knowledge of the Quartus software

Prerequisites

We recommend completing the following courses:

• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Partial Reconfiguration with Arria 10 FPGAs

Related Courses

Below are the related courses you may be interested in:

• Migrating to the Quartus Prime Pro Edition Software

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• FPGA Designers - Level 200

Class Schedule

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