As FPGA designs become more complex, a larger part of development time is spent verifying designs. This course introduces the various debug tools included in the Intel® Quartus® Prime software & shows effective ways to debug an FPGA design using them, decreasing overall design development time.
The class discusses the Signal Tap embedded logic analyzer, Signal Probe, In-System Sources & Probes, the Logic Analyzer Interface, System Console, and others. The class mostly focuses on Signal Tap, including hands-on lab exercises utilizing the tool in a real design.
At Course Completion
You will be able to:
- Completion of "The Quartus Software Design Series: Foundation" course OR a working knowledge of the Quartus software
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: