Using the Intel® Quartus® Prime Pro software version 19.1 and building upon your basic understanding of creating Synopsys* Design Constraint (SDC) files, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.
*Other names and brands may be claimed as the property of others.
At Course Completion
You will be able to:
- Write Tcl script files to automate constraining and analysis of FPGA designs
- Apply timing exceptions to real design situations
- Properly constrain and analyze the following design situations: source synchronous interfaces, external feedback designs, and high-speed interfaces containing dedicated SERDES hardware
- Experience with PCs and the Windows operating system
- Completion of "The Intel® Quartus® Prime Software Design Series
- OR "Timing Analysis with the Timing Analyzer" course
- OR a working knowledge of Timing Analzyer and basic SDC commands
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: