You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v. 20.3. This includes writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the Timing Analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the Timing Analyzer makes it easy to create timing constraints to help you meet those requirements.
Note: While the focus of this course is the Intel Quartus Prime Pro software, much of the flow and constraints are valid with the Subscription and Lite versions of the software.
At Course Completion
You will be able to:
- Understand the Timing Analyzer timing analysis design flow
- Apply basic and intermediate timing constraints to an FPGA design
- Analyze an FPGA design for timing using the Timing Analyzer
- Write and manipulate SDC files for analysis and controlling the Intel Quartus Prime software compilation
- Completion of The Intel Quartus Prime Software: Foundation online or instructor-led course OR a working knowledge of the Intel Quartus Prime software
- Understanding of basic hardware timing parameters and equations used in the timing verification OR completion of Introduction to Timing Analysis
We recommend completing the following courses:
Upon completing this course, we recommend the following courses (in no particular order):
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum: