Intel® Quartus® Prime Pro Software Timing Analysis (IDSW121)

8 Hours Instructor-Led / Virtual Class Course

Course Description

You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Intel® Quartus® Prime Pro software v. 20.3. This includes writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the Timing Analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the Timing Analyzer makes it easy to create timing constraints to help you meet those requirements.

Note: While the focus of this course is the Intel Quartus Prime Pro software, much of the flow and constraints are valid with the Subscription and Lite versions of the software.

At Course Completion

You will be able to:

  • Understand the Timing Analyzer timing analysis design flow
  • Apply basic and intermediate timing constraints to an FPGA design
  • Analyze an FPGA design for timing using the Timing Analyzer
  • Write and manipulate SDC files for analysis and controlling the Intel Quartus Prime software compilation

Skills Required

  • Completion of The Intel Quartus Prime Software: Foundation online or instructor-led course OR a working knowledge of the Intel Quartus Prime software
  • Understanding of basic hardware timing parameters and equations used in the timing verification OR completion of Introduction to Timing Analysis

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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Virtual Classroom (9:00am-1:30pm Pacific Time)10/20/2021 - 10/21/2021FreeRegister Now
Virtual Classroom (10:00 am-2:30 pm Central European Time CEST)11/08/2021 - 11/09/2021FreeRegister Now

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