The Quartus Prime Software Design Series: Timing Analysis

8 Hours Instructor-Led / Virtual Class Course

Course Description

You will learn how to constrain & analyze a design for timing using the timing analyzer in the Intel® Quartus® Prime software v. 17.1. This includes understanding FPGA timing parameters, writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion

You will be able to:

Understand the timing analyzer timing analysis design flow
Apply basic and complex timing constraints to an FPGA design
Analyze an FPGA design for timing using the timing analyzer
Write and manipulate SDC files for analysis and controlling the Intel Quartus Prime compilation