Course DescriptionLearn the timing-driven Simulink design flow for implementing high-speed DSP designs. This course is focused on the hands-on development of highly-optimized DSP algorithms using the advanced blockset capability of the latest DSP Builder—an interface between the Intel® Quartus® Prime software and Mathworks MATLAB & Simulink tools.
You will analyze and design your DSP algorithm using the DSP Builder for Intel FPGAs MATLAB and Simulink. You will learn how to easily explore architecture and performance tradeoffs with system-level constraints. You will also verify the functionality and the performance of the generated hardware in the Intel Quartus Prime software.
At Course Completion
You will be able to:
- Implement DSP algorithms using DSP Builder for Intel FPGAs
- Incorporate IP and Primitive cores in a design
- Explore design architecture and performance tradeoffs using system-level constraints
- Incorporate a DSP Builder model into a Platform Designer system
- Verify the hardware performance and implementation in the Intel Quartus Prime software
- Familiarity with DSP fundamentals and design
- Familiarity with Intel® Quartus Prime software is helpful, but not necessary
- Familiarity with Mathworks MATLAB and Simulink is helpful, but not necessary
- Familiarity with digital modem design is helpful, but not necessary
Upon completing this course, we recommend the following courses (in no particular order):
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Intel FPGA training curriculum:
No class is being offered at this time.