Transceiver PHY IP – Support Center

Welcome to the Transceiver PHY IP support center!

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

What's New

Intel® Stratix® 10 L-Tile and H-Tile Transceiver PHY User Guide

Intel® Advanced Link Analyzer Tool

Intel® Stratix® 10 Forward Error Correction

Which Intel® FPGA Device Family Should I Use?

Device		Intel® Cyclone® 10	Intel® Arria® 10			Intel® Stratix® 10
Table 1 - Device Variant and Feature Support
Device Variant		GX	SX⁽³⁾	GX⁽³⁾	GT⁽⁴⁾	GX/SX L-Tile	GX/SX H-Tile
Maximum Data Rate (Chip-to-Chip)⁽¹⁾⁽⁷⁾	GX Channels	12.5 Gbps	17.4 Gbps		17.4 Gbps	17.4 Gbps	17.4 Gbps
Maximum Data Rate (Chip-to-Chip)⁽¹⁾⁽⁷⁾	GXT Channels	N/A	N/A		25.8 Gbps	26.6 Gbps	28.3 Gbps
Maximum Data Rate (Backplane)⁽⁸⁾	GX Channels	6.6Gbps	12.5 Gbps		12.5 Gbps	12.5 Gbps	28.3 Gbps
Maximum Data Rate (Backplane)⁽⁸⁾	GXT Channels	N/A	N/A		12.5 Gbps	12.5 Gbps	28.3 Gbps
Maximum Channels per device	GX Channels	12	96		72	96	96
Maximum Channels per device	GXT Channels	N/A	N/A		6	32	64
Hard IP		One PCIe Gen2 x4 per device.	PCIe* Gen3 x8 up to 4 per device			PCIe Gen3 x16 up to 4 per device	50/100 Gbps Ethernet MAC up to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) ⁽⁶⁾
Hard IP		SR-IOV support is not available.	PCIe* Gen3 x8 up to 4 per device			PCIe Gen3 x16 up to 4 per device

The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel^® Arria^® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel^® Arria^® 10 Device Datasheet.
Intel^® Arria^® 10 and Intel^® Stratix^® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications.
For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications.
Intel^® Stratix^® 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel^® Stratix^® 10 L-/H-Tile Transceiver PHY User Guide.
SR-IOV stands for Single-Root Input Output Virtualization.
Intel^® Arria^® 10 and Intel^® Stratix^® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.

Intel® FPGA Device Datasheets

Additional Resources

Refer to the Overview chapter of the following user guides:

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 Transceiver PHY User Guide

Intel® Arria® 10 Devices

Intel® Arria® 10 Transceiver PHY User Guide

Intel® Stratix® 10 Devices

Where Can I Find Information on Transceiver Usage?

Use the E-Tile Channel Placement Tool in conjunction with the Intel® Stratix® 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software.The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs.

What Design Recommendations Should I Consider?

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Device Errata and Design Guidelines

Intel® Arria® 10 Devices

Where Can I Find Information on Transceiver PHY IP Integration?

Intel® Cyclone® 10 Devices

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

Where Can I Find Information on the Transceiver PHY IP Register Mapping?

Intel® Cyclone® 10 Devices

Logical View of the Intel® Cyclone® 10 Transceiver Registers

Intel® Arria® 10 Devices

Logical View of the Intel® Arria® 10 Transceiver Registers

Intel® Stratix® 10 Devices

Logical View of the Intel® Stratix® 10 L- and H-Tile Transceiver Registers

Analog Settings Guidelines

Intel® Cyclone® 10 and Arria® 10 Devices

Intel® Cyclone® 10 and Arria® 10 Pre-emphasis and Output Swing Estimator

Intel® Stratix® 10 Devices

Intel® Stratix® 10 L-Tile/H-Tile Pre-emphasis and Output Swing Estimator

Additional Resources

Board Design Guidelines

Pin Connection Guidelines

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

Intel® Arria® 10 Devices

Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel® Stratix® 10 Devices

Intel® Stratix® 10 Device Family Pin Connection Guidelines

Schematic Review

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Schematic Review Worksheet

Intel® Arria® 10 Devices

Intel® Arria® 10 GX, GT, and SX Schematic Review Worksheet

Intel® Stratix® 10 Devices

Intel® Stratix® 10 GX, MX, and SX Schematic Review Worksheet

Power Management

Simulation Models & Tools

Intel ® Advanced Link Analyzer

The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.

Models

Development Kit User Guides

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

Applications

AN 835: PAM4 Signaling Fundamentals

AN 846: Intel® Stratix® 10 Forward Error Correction

Models

IEEE 1149.6 BSDL Files

Design Examples

Design Examples and Reference Designs

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 Transceiver PHY Basic Design Examples (Intel Forums)

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

High Speed Transceiver Demo Designs - Stratix 10 Series

Recommended Training Courses

Title	Type	Description
Building Interfaces with Arria® 10 High-Speed Transceivers	Instructor-Led	Learn the architecture of Intel® Arria 10 and Intel Cyclone® 10 FPGA transceivers and then the flow for incorporating them into an FPGA design.
Transceiver Basics for 20 nm and 28 nm Devices	Online	Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols.
Stratix® 10 Transceiver Basics	Online	Learn the basic building blocks that are found in Intel Stratix® 10 FPGA transceivers used to support a range of high-speed protocols.
Transceiver Toolkit for Arria® 10 Devices	Online	Learn how to debug and dynamically fine tune the analog settings of your Intel® Arria® 10 and Intel® Cyclone® 10 FPGA transceivers.
Advanced Signal Conditioning for Arria® 10 FPGA Transceivers	Online	Learn the analog capabilities of Intel® Arria® 10 FPGA transceivers and how to use them to improve link performance.
Building a Generation 10 Transceiver PHY Layer	Online	Learn how to build a custom transceiver implementation using the Intel® Arria® 10 and Intel® Cyclone® 10 FPGA transceiver IP blocks.
Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer	Online	Learn how to define the three resources that make up an Intel® Stratix® 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller.
Generation 10 Transceiver Clocking	Online	Learn the clocking resources that are found in Intel Arria® 10 and Intel® Cyclone® 10 FPGA transceiver blocks.

Other Training Courses

Transceiver Training Courses

Title	Description
How to Dynamically Reconfigure PMA Analog Parameters for Intel® Cyclone® 10 GX	Learn the implementation of Intel® Cyclone® 10 GX FPGA Native PHY PMA analog parameters using direct reconfiguration flow.
How to Perform the Intel® Cyclone® 10 GX Dynamic Reconfiguration with fPLL Switching and Channel Reconfiguration Using Direct Write Method	Learn how to perform the transceiver dynamic reconfiguration functional simulation with Intel® Cyclone® 10 GX FPGA fractional phase-locked loop (PLL) switching and channel reconfiguration using the direct write method.
How to Perform Intel® Cyclone® 10 GX Native PHY ATX PLL Switching and Channel Reconfiguration	Learn how to perform the functional simulation with Intel® Cyclone® 10 GX FPGA Native PHY ATX PLL switching, channel reconfiguration with embedded streamer, and channel recalibration.
How to Switch the CDR refclk Selection Using Embedded Streamer and Reconfiguration Profiles in Arria® 10 Native PHY	Learn how to perform dynamic reconfiguration to switch the clock data recovery (CDR) refclks with embedded streamer and multiple reconfiguration profiles in the Intel® Arria® 10 device.
How to Configure Two FPGAs that is Externally Connected through SMA Cables Using Transceiver Toolkit	Learn how to how to configure two device under test (DUTs), launch transceiver (XCVR) toolkits, perform chip-to-chip interface, and find the right analog settings.
How to Perform Dynamic Reconfiguration to Switch TX PLLs for the Arria® 10 Transceiver Using Embedded Streamer	Learn how to perform dynamic reconfiguration to switch transmitter (TX) PLLs for the Intel® Arria® 10 FPGA transceiver using embedded streamer.

Title	Description
Intel® Arria® 10 Device Configuration of a Simplex Transceiver	Watch this video to learn how to place an Intel® Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.
Dynamic Reconfiguration of an Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel® Arria® 10 devices.
How to Use the Transceiver Toolkit Part 1	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.
How to Use the Transceiver Toolkit Part 2	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 3	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 4	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
Intel® Arria® 10 Transceivers: Pre-Emphasis Basics	Learn the basics of the Intel® Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.
Performing Dynamic Reconfiguration for the Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel® Arria® 10 devices.
Reconfigure Intel® Arria®10 Device Transceivers Using Embedded Streamer	Watch this video to learn how to perform dynamic reconfiguration with the Intel® Arria® 10 device transceiver Standard PCS using the embedded streamer.
Use the IBIS-AMI Model to Estimate Signal Integrity of Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform a signal integrity simulation with the Intel® Arria® 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.

Title
Intel® Stratix® 10 SX Device Features
Do Altera transceivers support single-ended communication?
Can the transceiver PHY in Gigabit Ethernet mode compensate for clock frequency differences between the recovered clock and the reference clock during 1000BASE-X/SGMII auto-negotiation?
Are the SerialLite II and SerialLite III IP protocols compatible?
Is 8b10b encoding supported in the Arria V, Cyclone V or Stratix V transceiver toolkit?
Why might the Arria V, Cyclone V, or Stratix V device Transceiver Toolkit TCL scripts not work properly?
Are the SerialLite I and SerialLite II IP protocols compatible?
Why does my Arria V, Cyclone V, or Stratix V device Transceiver Toolkit design show a greyed out System Console panel when using Quartus II software version 14.0?
Why does my Avalon Memory Mapped bus hang when accessing the transceiver reconfiguration controller in Arria V, Cyclone V and Stratix V devices?
Can I use generic parameters with transceiver MegaWizard generated files to create multiple transceiver MIF file variations for Altera transceivers?
Where can I get board simulation models for REFCLK pins using HCSL or other I/O standards?
Why does transceiver reconfiguration fail for Arria V, Cyclone V, and Stratix V devices when I use a reduced MIF file generated with the Quartus II software version 14.0 and earlier version of the xcvr_diffmifgen.exe tool?
Error: Unresolved defparam somewhere
Can I simulate the CMU or CDR frequency tracking function with Altera transceiver simulation models?
Why doesn't the "set_parameter -name pma_bonding_master" Quartus Settings File (.qsf) assignment have an effect in the Quartus II software version 13.0sp1 for Arria V, Cyclone V, or Stratix V devices?
Why can't I place a reference clock for transceivers on the GXB_RX / GXB_REFCLK input?
Why is there an increase in measured transceiver VCCL_GXB and VCCR_GXB current for a design compiled in Quartus II software versions 13.0, 13.0sp1. 13.1, and 13.1sp1 for Cyclone V, Arria V, and Stratix V transceiver devices?
What are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices?
Why do I see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the transceiver reconfiguration controller when using Stratix V, Arria V, or Cyclone V transceiver devices?
How can I resolve Quartus II software "HSSI_PMA_AUX" associated fitter errors when compiling with Stratix V, Arria V, and Cyclone V transceiver devices?
What is the correct number of reconfiguration interfaces required for a XAUI PHY IP when using Stratix V, Arria V, and Cyclone V transceiver devices?
What is the address of the "Write to the 'write' bit of the control and status register" in "Table 8: Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" of AN676?
Why does the tx_datak signal refer to received data for the Arria V, Cyclone V and Stratix V devices in the Altera Transceiver PHY IP User Guide?
Why does my Arria V, Cyclone V, or Stratix V device Transceiver Toolkit design fail to lock when using Quartus II software version 14.0?
Warning (332056): PLL cross checking found inconsistent PLL clock settings
How do I disable Pre-CDR or Post-CDR Reverse Serial Loopback on Stratix V, Arria V, and Cyclone V transceiver devices?
What are the typical rules for sharing a Tx PLL between multiple transceiver instances on Stratix V, Arria V, and Cyclone V transceiver devices?
Why can t I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices?
How can I connect two Transceiver Toolkit System Consoles to two Altera devices with two USB ports on the same computer, when each device is programmed with the same FPGA image?
Why can't I merge multiple SDI IP instances sharing a single Tx PLL when implementing the triple standard protocol on Stratix V, Arria V, and Cyclone V transceiver devices?
What are the definitions of the dedicated transceiver refclk pin XCVR_REFCLK_PIN_TERMINATION QSF assignments for Stratix V, Arria V, and Cyclone V transceiver devices?
Can I use single MIF file for Altera transceiver devices running at different data rates?
Fitter failed to read .mif file: db/reconfig_map_0.mif
Where can I find Active Bit information for the Stratix V, Arria V, and Cyclone V transceiver Native PHYs?
Why are X's displayed on the reconfig_to_xcvr and reconfig_from_xcvr busses between my Reconfiguration Controller and transceiver PHYs in simulation of Stratix V, Arria V, and Cyclone V transceiver devices?
Can I directly connect (DC-couple) TMDS or LVPECL devices with Altera transceivers?
What is the correct XCVR_RX_SD_ENABLE QSF variable setting to turn ON/OFF the signal detect fetaure in Stratix V, Arria V and Cyclone V devices?
Why cant I use a transceiver recovered clock to feed a transmitter PLL reference clock on Altera transceiver devices?
Can I use the INPUT_TERMINATION .qsf assignment to assign an on-chip termination (OCT) to Transceiver REFCLK or Transceiver IO pins, in Stratix V, Arria V and Cyclone V devices?
Why does the Arria V GX and Cyclone V GX device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus II software version 13.1?
Critical Warning (184043): Fitter was unable to find transceiver reconfiguration controllers
Do Stratix II GX HSPICE models include REFCLK pin models, If not, how can I simulate the REFCLK pin?
Are the Pre-CDR and Post-CDR Reverse Serial Loopback PMA Offset registers write only on Stratix V, Arria V, and Cyclone V transceiver devices?
What output clock should I connect to the Native PHY IP when using a fPLL as a transceiver Tx PLL on Stratix V, Arria V, and Cyclone V transceiver devices?
Why are the VOD, pre-emphasis, and slew rate parameters reported as -1 for Stratix V, Arria V, and Cyclone V transceiver pins in the Resource Property Editor when using Quartus II software version 13.0 and 13.0sp1?
Can I connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP?
Why doesn't pulsing transceiver edge sensitive input signals have an effect in Cyclone V, Arria V and Stratix V transceiver devices?
Are there any additional steps required when archiving a transceiver toolkit design with Quartus II software versions 12.0 or later?
Error: Clock Divider node 'inst\|altera_xcvr_native_av:txcvr_top_inst\|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst\|av_pma:inst_av_pma\|av_tx_pma:av_tx_pma\|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst\|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port.
Why don't I see an difference in simulation results when I change the Tx drive strength settings of the IBIS-AMI transceiver models?
Why is a reconfig_mif file not generated during compilation of my design containing a bonded mode transceiver instance for Stratix V or Arria V devices?
Can I connect unused GXB_RX pins to GND in Arria V and Cyclone V devices?
When should I use the cal_blk_powerdown signal to calibrate the transceiver on-chip termination?
What is the reset sequence for high speed GX transceivers in loss of link conditions in Altera GX/GT/GZ device families?
Error (178018): Channels in the bonded channel groups containing the following must be placed in contiguous locations. If CMU PLLs are used, gaps must be left for the transmit PLL channel.
What version of Mentor Graphics Hyperlynx should I use to simulate with Altera transceiver IBIS-AMI models?
Are there any recommendations when using more than one ATX PLL that run at the same Voltage Controlled Oscillator (VCO) frequency in Arria V GZ and Stratix V transceiver devices?
Error (21087): Input port "CALCLK" must be driven by the same source
Does the word aligner detect both positive and negative disparity patterns in Stratix, Arria, and Cyclone transceiver devices?
At what stage in the Quartus II compilation process are the MIF files generated for Stratix V, and Arria V devices using transceiver dynamic reconfiguration?
Error (12252): Link_test_sopc_sys.clk.clk_reset/checker_0.csr_clk_reset: Missing connection end (try "Remove Dangling Connections")
Why do I see increased low frequency jitter when using the ATX PLL of Stratix V or Arria V GZ transceiver devices?
Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?
Why are there bit errors when I perform an RTL simulation of an external serial loopback on Stratix V and Arria V transceiver devices?
Can a single fPLL output be used as a transceiver reference clock and also drive logic within the fabric on Stratix V GX, Arria V GX, and Arria V GZ devices?
Why might an Arria V, Cyclone V or Stratix V device transceiver not work correctly when an fPLL is used as a Tx PLL as well as a general purpose PLL?
How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices?
Can I leave unused transceiver receivers unconnected for Stratix V GX/GS/GT, Arria V GX/GT and Cyclone V GX devices?
altera_xcvr_custom:phy_inst\|av_xcvr_custom_nr:A5\|*\|avmm_interface_insts[0].av_hssi_avmm interface_inst~BURIED_ASYNC_DATA_OUT
What are the recommended SATA/SAS Signal Detect Preliminary Settings for Arria V GT/GX/ST/SX and Cyclone V GX/SX devices?
How do I transmit XAUI compliant data using Altera transceivers?
Error: TX PMA element 'altgx_xaui:inst\|altgx_xaui_alt4gxb:altgx_xaui_alt4gxb_component\|transmit_pma3' has an illegal SLEW_RATE
How do I turn on the 'offset_cancellation_reset' port on the Dynamic Reconfiguration Controller MegaWizard for Stratix IV GX/T, Arria II GX/Z, and Cyclone IV GX devices?
Can I turn off the transceiver power rails, if none of the transceivers are used?
Warning 12283 – Assignment INPUT_TERMINATION on transceiver refclk clk buf/pin pcie_ref_clk is not supported
How do I modify the "Starting Channel Number" parameter in a Qsys-Generated RapidIO transceiver instance?
Why do I see Arria V GZ and Stratix V GX device ATX PLL performance problems at temperature extremes when configured to run at datarates of 10.5 - 12.3 Gbps?
How do I transmit START, TERMINATE, and ALIGN code groups from the transceiver when configured in XAUI mode for Stratix, Arria, and Cyclone transceiver devices?
Why are the xgmii_rx_dc[71:0] and xgmii_rx_clk signals not synchronized to rx_coreclkin during simulation of the 10GBASE-R PHY IP in Stratix V GX devices when using Quartus II Software version 12.0?
What is the state of unused transceiver transmit pins on Stratix IV, Arria II, and Cyclone IV devices?
Does the ATX PLL support the High Bandwidth setting in Stratix V GX and Arria V GZ devices?
Error (175005): Could not find a location with: PMA_DIRECT_CHANNEL
Error: Clock Divider node 'inst\|altera_xcvr_native_sv:txcvr_top_inst\|sv_xcvr_native:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst\|sv_pma:inst_sv_pma\|sv_tx_pma:tx_pma.sv_tx_pma_inst\|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst\|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port.
Does the transceiver reference clock need to be stable before ATX PLL calibration is performed on Stratix V GX/T and Arria V GZ devices?
Why does the Arria V GZ and Stratix V device Transceiver PLL Megawizard show a "Dynamic reconfiguration of ATX PLLs is not supported in the current release" message when you hover your cursor over the "Enable PLL reconfiguration" option in Quartus® II software version 13.1?
What are the legal TX common mode voltage QSF assignments when using the 1.5-V PCML I/O Standard for Stratix V GX/GT and Arria V GZ devices?
Why does the 'RX CDR PLL status' indicator show 'PLL not locked' on the Transceiver Toolkit when the 'RX CDR data status' indicator shows 'PLL locked' and data is being received correctly?
Why does the recommendation for the connection of the unused GXB_RX and GXB_REFCLK pins disagree between the Stratix V and Arria V GZ pin connection guidelines documents and the Quartus II software .PIN files?
Why doesn't the rx_eqctrl_out value of the altgx_reconfig Megawizard change after channel reconfiguration in Cyclone IV GX, Arria II GX, Arria II GZ, Stratix IV GX/GT and Hardcopy IV devices?
Can I use the transceiver Reconfiguration Controller's Avalon PLL Reconfiguration registers to switch between ATX PLL reference clocks on Stratix V GX/GT and Arria V GZ devices?
For a given data rate, which frequency will provide the best jitter performance for the high speed transceiver CMU PLL of a GX devices?
Why can't I use the x1 line to clock Arria V device transceiver channels higher than 6.5536 Gbps within a transceiver bank but across a triplet boundary when using Quartus II software version 15.0.1 and earlier?
Have there been any changes in Quartus II 12.1 when merging Transceiver TX PLLs if PLL/CDR Reconfiguration has been enabled in Stratix V GX devices?
Is the on-chip biasing network of the REFCLK input pin in Altera transceiver based devices enabled before or during device configuration?
Why doesn't the Native PHY compensate for clock frequency differences on Stratix V GX devices using Quartus II software versions 12.1sp1 and earlier?
Over what frequency range do I need 60dB isolation between the VCCR_GXB and VCCT_GXB power supplies, in Stratix V GX, GS, and GT devices?
Why is received data getting corrupted when reconfiguring from a bonded mode using the ratematch block to a bonded mode not using the ratematch block?
Why does CMU PLL loose lock in bonded configuration before busy signal is de-asserted in Arria II GX/GZ, Stratix IV GX/GT and Hardcopy GX devices?
Error (11574): ATX PLL node &lt;ATX PLL node name&gt; uses an output frequency of &lt;configured data rate&gt; MHz that exceeds the maximum frequency of 13200.0 MHz in the targeted speed grade <device speed grade> for a Bottom ATX PLL in a transceiver bank
Error (175001): Could not place HSSI_PMA_AUX &lt;instance path&gt.sv_tx_pma_ch_inst\|tx_pma_ch.tx_pma_buf.tx_pma_aux
What is the latency of the transceiver rx_syncstatus signal de-asserting after the assertion of the rx_enapatternalign signal in Stratix IV GX/T, Arria II GX/Z and Cyclone IV GX devices?
Can I leave unused transceiver receivers unconnected for Stratix IV GX/ GT, Arria II GX/GT and Cyclone IV GX devices?
Why do I see transceiver functionality problems when a transceiver reconfiguration controller is connected
Why are additional transceiver banks available in my Cyclone V device?
What clock domain are the rx_hi_ber and rx_block_lock signals of the 10GBASE-R PHY IP synchronous to?
Why does the Offset Cancellation busy signal de-assertion duration in the ALTGX_RECONFIG block simulation does not match with the duration information in the device handbook?
Why do I see incorrect transceiver dynamic reconfiguration behavior when using Quartus II software version 14.1 of the Native PHY IP core for Arria 10 devices?
Why don't I see any difference in the transceiver Quartus II Power Play Power Analyzer results when I enable the EyeQ feature on Stratix V GX/T and Arria V GZ devices?
Why do I see excessive receiver latency when using the Low Latency or Native PHY, 10G PCS Basic mode on Stratix V GX or Arria V GZ devices?
Error: xcvr: set_port_property sets an illegal FRAGMENT_LIST for port unused_tx_parallel_data
Can I interleave the transceiver channel placement of the Interlaken 100G IP when using Stratix V transceiver devices?
Why do I see timing violations in the Stratix V and Arria V GZ device Reconfiguration Controller IP when the Bit Error Rate block is enabled?
Are any combinations of Stratix V GX/GT transceiver PMA transmitter analog settings illegal?
Can I supply VCCA_GXB[L,R] with 2.5V if I intend to use ATX PLLs on Stratix V GX, GS, and GT devices?
Error (175001): Could not place Transmitter channel
Are there any differences in behaviour between RTL simulation and hardware when implementing Rx CDR PLL dynamic reconfiguration using the direct write method of Stratix V devices?
Why the pll_locked signal is always low in the SignalTap II file?
Error (12848): "REF10GCLK" is locked to right side. There is no HSSI strip on right side.
What is the correct receiver dc gain range for the XCVR_RX_DC_GAIN qsf variable in Cyclone V transceiver devices?
Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic.
Error: Channel PLL Parameter 'output_clock_frequency' is set to an illegal value of '<Channel PLL output frequency> MHz' and PMA Direct parameter is set to 'false'.
Error:invalid command name "altgx_mifgen"
How long does the transceiver on-chip termination calibration process take for Stratix IV GX/T and Arria II GX/Z devices?
Why doesn't the Reverse Serial Loopback (RSL) feature work on Arria V GX devices in Quartus II Software versions 12.1sp1 and earlier?
Warning (113009): Data at line (n) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
How can I meet the Stratix V and Arria V GZ device ATX PLL calibration requirement that the transceiver reference clock must be present at the start of device configuration if I use the FPGA to program my clock synthesizer device?
Why does my Arria 10 fPLL output an incorrect clock frequency or misaligned clocks?
Why is the dedicated transceiver refclk pin Vicm lower than the specification in the Arria V GX device datasheet when using Quartus II software versions 12.1sp1 and earlier?
Do rx_analogreset and rx_digitalreset inputs affect rx_signaldetect status in Cyclone IV GX and other GX/GT/GZ device families?
Are there any conditions where the transceiver CMU PLL may fail to lock after CMU PLL reconfiguration in Stratix IV GX/GT, HardCopy IV GX, and Arria II GX/GZ devices?
why you get Error(11997): Design has 55 tx channels, 9 rx channels, exceeds the capacity of targeted device, 48 channels?
Why are the RREF pins shown as GND in Arria 10 .pin files?
How can I enable RX Phase Comp FIFO in register mode option in the ALTGX MegaWizard in Quartus II software version 9.0 SP2 for Stratix IV GX, Stratix IV GT and Arria II GX devices?
How do I map the 8 available transceiver VOD settings in the Stratix V GX IBIS-AMI model to the 64 available settings in the Custom and Low Latency PHY MegaWizards, and Transceiver Toolkit?
How do I calculate DFE power consumption using the Quartus II Power Play Power Analyzer (PPPA) and Early Power Estimator (EPE) for Stratix V and Arria V GZ devices?
Is external termination required by Stratix V devices to interface with SFP+ Optical modules?
In simulation of the Stratix V Reconfiguration Controller, why do my ATX Calibration Registers all read "DEADBEEF"?
Are there any known issues with the transceiver rx_eqdcgain PMA control in Stratix IV GX and Arria II GX devices?
Error:xxx: The current value "" (2970) for parameter "PLL output frequency" (output_clock_frequency) is invalid. Possible valid values are: "" (3000.0:12500.0). . Rule(s): output_clock_frequency.
Error (11176): Alt_sld_fab.alt_sld_fab.stfabric.demux: "Number of Output Ports" (numOutputInterfaces) &lt;Number of Channels&gt; is out of range: 1-16
How do I map the Quartus Prime software and IBIS-AMI model slew rate settings for Cyclone V devices?
How can I recalibrate the Stratix V and Arria V GZ device ATX PLLs?
Error (11686): Your design contains more than two ATX (LC) PLLs in the same HSSI transceiver bank
Why don't I see any difference in the transceiver Quartus II Power Play Power Analyzer results when I enable Adaptive Equalization on Stratix V GX/T and Arria V GZ devices?
Why does the Transmitter PLL and/or CDR not lock after power-up in Stratix IV and Arria II GX Transceivers.
Why can't I enable the rx_patterndetect signal on the Custom PHY when in bit slip mode for Arria V GX and Stratix V GX devices?
Why can't I implement more than one transceiver PHY instance in a transceiver block with Stratix IV GX/T or Arria II GX Transceiver Toolkit designs?
Critical Warning: Fitter was unable to find Transceiver Reconfiguration Controllers associated with the following &ltnumber of transceiver blocks&gt transceiver PHY IP component blocks.
Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GZ and Stratix V devices?
Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Cyclone V devices?
Error: inst: The maximum data rate for this configuration is nnn.n MHz
Why is support for the 10GBASE-KR, 10GBASE-R and 1G/10GbE PHY IP Cores for Arria V and Stratix V devices listed as preliminary in the Altera Transceiver PHY IP Core User Guide?
Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria V GZ, and Stratix V GX/GT devices?
How can I enable transceiver polarity inversion in the 10GBASE-R PHY IP for Arria V GZ and Stratix V GX devices?
Critical Warning: parameter 'crcchk_init' of instance '...\|sv_hssi_10g_rx_pcs_rbc' has illegal value '' assigned to it. Valid parameter values are: '(crcchk_int)'. Using value 'crcchk_int'
What are the legal TX common mode voltage QSF assignments when using the 1.5-V PCML I/O Standard for Arria V GX/GT and Cyclone V GX/GT devices?
Can I place bonded transceiver channels non-contiguously in Stratix V and Arria GZ transceiver devices?
Can timing violations for the pif_interface_sel signal be safely ignored for the Stratix V and Arria V GZ device transceiver Reconfiguration Controller when compiled in Quartus II software, version 12.1?
Why do I see warning messages when simulating a Native PHY with 10G PCS PRBS pattern generator and verifier enabled on Arria V GZ or Stratix V GX devices?
Are there any problems with version 13.1 of the JNEye tool when modelling the receiver of Arria 10 GX/T devices?
What is the correct transceiver reference resistor (RREF) value for Arria 10 devices?
Why does transceiver dynamic reconfiguration fail when the "Enable continuous write of all the words needed for reconfiguration" option is enabled in the altgx_reconfig MegaWizard on Stratix IV GX/T and Arria II GX/GZ devices?
Are there any channel placement restrictions when implementing bonded transceiver channels using the Quartus II Software for Stratix V GX, GS, and GT devices?
Are there any known issues with the "Use external receiver termination" option in the altgx Megafunction?
Can I start a new read or write process on the ALTGX_RECONFIG IP when the busy signal is high on Stratix IV GX/T, Arria II GX/Z, and Cyclone IV GX devices?
Will the receiver side of a transceiver channel be available during ATX PLL calibration of Stratix V GX/GT and Arria V GZ devices?
Is there any known issue in using the 'data rate division in TX' feature available in the dynamic reconfiguration controller for Stratix IV / Arria II GX transceivers.
Can I drive more than one transceiver reference clock input from an fPLL via the cascade clock network on Cyclone V GX devices?
Since I am only using the Stratix II GX RX portion in my transceiver design, do I need to connect the VCCH power pins for the TX buffers?
Why does Quartus II assigns incorrect I/O standard for the refclk pin on Arria II GX/GZ and Stratix IV GX/GT devices for ALTGX instances?
Warning: <fPLL instance name>.xcvr_fpll_a10_0: The value of parameter cmu_fpll_pll_n_counter_coarse_dly cannot be automatically resolved. Valid value ranges are: {0 ps} {200 ps} {400 ps} {600 ps} {800 ps} {1.0 ns}.
Why can't I reconfigure the ALTGX instance in Stratix IV GX/GT and Arria II GX devices, when I enable both "Data Rate Division in TX" and "Channel and TX PLL select/reconfig" modes in the ALTGX_RECONFIG block?
Are there any problems with transceiver reduced MIF dynamic reconfiguration in Stratix IV and Arria II devices?
Error (14024): Parameter "sd_threshold" of instance "gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd" has illegal value "3" assigned to it. Possible parameter values are: "SDLV_15", "SDLV_14", "SDLV_13", "SDLV_12", "SDLV_11", "SDLV_10", "SDLV_9", "SDLV_8", "SDLV_7", "SDLV_6", "SDLV_5", "SDLV_4", "SDLV_3", "SDLV_2", "SDLV_1", "SDLV_0"
Why does the ATX PLL REFCLK switching not work in simulation when using the Stratix V GX Custom or Low Latency PHY in Quartus II Software version 12.0?
Can I power down VCCH_GXB pins of Arria 10 devices when I do not use the whole side of the transceiver banks?
What is the transceiver channel numbering scheme within a bank for Stratix V transceiver devices?
Error: Clock Divider parameter 'data_rate' is set to an illegal value of 'xxxx.x Mbps' on node 'native_phy_top:inst \|altera_xcvr_native_sv:native_phy_top_inst \|sv_xcvr_native:gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst \|sv_pma:inst_sv_pma\|sv_tx_pma:tx_pma.sv_tx_pma_inst \|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst\|tx_pma_ch.tx_cgb'. Info: "xxx.x Mbps" is a legal value
Why does the Quartus Prime Pin Planner show a transceiver dedicated reference clock pin on the right side of an Arria 10 device that only has transceiver channels on the left side?
Error (14498): Arria 10 devices have specific voltage requirements for VCCR_GXB/VCCT_GXB Voltage pins.
Error (13119): Channels xxx are driven by X1 clock network and need to be placed in the same six-pack due to user location constraints. However, only 2 of the six-pack channels are usable.
How do I resolve timing failures on the Stratix V GX Reconfiguration Controller IP pmatestbussel bus when I recompile my design in Quartus II software version 13.0?
Why do I see the following Qsys warnings when I open a Quartus II 13.0sp1 version of a Stratix IV GX/T Transceiver Toolkit example design?
Why do I see bit errors on Rx channel 0 of transceiver block GXBL1 when I de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone IV GX EP4CGX150 and EP4CGX75 devices?
Why am I not able to perform bonded mode dynamic reconfiguration following instructions in AN 558: Implementing Dynamic Reconfiguration in Arria II GX devices?
How can I meet the Arria 10 device transceiver calibration requirement that the reference clock must be present at the start of device configuration if I use the FPGA to program my clock synthesizer device?
Are there any known issues forcing the 8b10b disparity through channel interface?
Warning: xxx.xcvr_native_a10_0: The current value "1_1V" for parameter "VCCR_GXB and VCCT_GXB supply voltage for the Transceiver" (anlg_voltage) is invalid. Possible valid values are: "1_0V" "0_9V". The parameter value is invalid under these current parameter settings: "device" (device)="" (10AX115S4F45I3SGE2). Rule(s): pma_rx_buf_power_mode: pma_tx_buf_power_mode: pma_rx_buf_power_mode_rx.
How do I map the Quartus® II and IBIS-AMI model slew rate settings for Stratix® V GX and Arria® V GZ devices?
Can I use dynamic reconfiguration to switch from XAUI to PCI Express Gen 2 in Stratix IV GX and GT devices?
How do I map the transceiver toolkit pre-emphasis pre-tap settings to the Quartus II transceiver QSF assignments in Stratix V GX and Arria V GZ devices?
Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_error_message.cpp, Line: 1559 PLL not found for channel implied by HSSI_TX_CHANNEL_CLUSTER0
Why doesn't my Quartus II XCVR_RX_LINEAR_EQUALIZER_CONTROL QSF assignment have any effect on the Stratix V GX equalizer in Quartus II software versions 12.1 and 12.1sp1.
Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly?
Does the transceiver Transmitter REFCLK Phase Noise specification in the Stratix 10 Datasheet refer to the differential phase noise, or to the maximum single-ended phase shift?
Why can’t the Quartus II software automatically merge the Transceiver Avalon Memory-Mapped interfaces of a CDR/CMU PLL and a TX-only channel, of an Arria 10 device?
Can I drive dedicated transceiver REFCLK pins during power up and down sequencing on Arria 10 devices?
Are Stratix V transceiver Quartus Settings File (.qsf) settings supported in Arria 10 devices?
Should I use word or byte addressing for Arria 10 device transceiver or Tx PLL IP implemented inside a Qsys system?
Are external AC coupling capacitors required when connecting transceivers to SFP+ modules?
Can I use Quartus II Transceiver Toolkit to test the high speed transceiver links between two different devices on two different boards?
How do I map the transceiver toolkit pre-emphasis 2nd post-tap settings to the Quartus II transceiver QSF assignments in Stratix V GX and Arria V GZ devices?
Why does the Arria 10 device Transceiver PHY User Guide (PDF) describe the tx_datak signal as '1' for a data word and '0' as a control word?
Why does the Quartus II fitter report display "unused" in the Termination column when applying the LVDS I/O standard to REFCLK pins in Arria ® 10 devices?
Are there any known problems with rxvalid occasionally deasserting when the Rate Match FIFO performs a SKP insert operation when using Gen3 soft PIPE on Stratix V GX devices?
Error (175001): Could not place LC_PLL_CHANNEL_CLUSTER
Why does my Stratix IV GX or Stratix IV GT design configured in Basic (PMA-Direct) mode not meet timing even if the left/right PLLs is implemented.as recommended in the Stratix IV Handbook, stratix_iv_gx_ki, stratix_iv_gt_ki
Why is the pll_powerdown port of the Stratix V device Transceiver Native PHY IP Core not removed when I enable the Use external TX PLL option?
Why does the Stratix V device Transceiver Toolkit display a "Couldn't grab settings for channel" message when using Quartus II software versions 14.1 and 14.1.1?
Error: ATX PLL parameter 'output_clock_frequency' is set to an illegal value
Can I safely ignore DIV_CLK critical warnings for the fPLL when used in the 66:40 gearbox ratio on Stratix V GX/GS/GT and Arria V GZ transceivers?
Why does the Quartus II software not create transceiver MIF files for Cyclone®, Arria® V, and Stratix® V devices with "advanced" or "inital" support?
What transceiver slew rate settings are allowed in the Quartus II software for Stratix V GX and Arria V GZ devices?
Why do I see a "System.xcvr: "Number of lanes" (lanes) (1) out of range (1,0)" Qsys error when upgrading Stratix IV GX and Arria II GX transceiver toolkit designs between different versions of the Quartus II software?
Can I invert the transciever Tx polarity with a signal port when using the Stratix V device, Native PHY IP, 10G PCS?
Is the DFE_control register a Read (R) or Write (W) location in Stratix V GX, GS, and GT devices?
Can I use REFCLK pin to generate reconfiguration clock (reconfig_clk) in Stratix IV GX/GT and Arria II GX devices?
Are there any known issues with pipe_pclk being inactive if txclkout is not routed through a global clock network when using Gen3 soft PIPE in Quartus II software version 12.1 on Stratix V GX devices?
Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria V GX/GT devices?
Are there any problems with Adaptive Equalization (AEQ) in Stratix IV GX and GT devices?
What can I do if the ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria II, Cyclone IV, or Stratix IV transceiver devices?
Why is the Stratix V GT device receiver parallel data output incorrect when using Quartus II software versions 14.0 to 15.0?
Why can't I generate a reduced MIF file with altgx_diffmifgen.exe for an Arria II GX TX only instance?
Internal Error: Sub-system: CUT, File: /quartus/db/cut/cut_stratixv_lc_pll_group.cpp, Line: 132 altera_xcvr_low_latency_phy
Why might the PCI Express signal detect feature fail at low temperatures on Arria V GT and ST devices and the link fail to train?
Warning: Cannot find PHY IP instance. MIF file is not generated for atom.
Why do I see timing violations when using the Arria V 10GBaseR PHY soft PCS?
Why are the Stratix V GX RX equalization settings different between the register mapped area, and the QSF assignments?
Are there any extra requirements when performing dynamic reconfiguration of the CMU PLL to data rates above 4Gbps in Arria V GX ES devices?
Why jittery transmitter output is observed in 10G Base R PHY IP for Stratix IV GT?
Where can I find AN580 Tcl scripts for PMA Direct timing closure in EP4SGX110 and EP4SGX360 Stratix IV GX devices?
What is the recommended input clock jitter for transceivers in Arria GX family devices?
Why does rx_analogreset input from FPGA fabric not have an effect on rx_freqlocked and rx_pll_locked signals in a Basic (PMA-Direct) channel implemented in CMU channel of the Stratix IV GX/GT or Hardcopy IV GX/GT devices?
Does Word Aligner in Stratix IV GX ALTGX Basic mode require continuous word alignment pattern to reach sync state?
Can a 9-transceiver channel Arria V GT device support an Rx only channel that already has four 6.144-Gbps duplex or Tx channels?
How can I identify the number of transceivers available in my Stratix IV GX device?
Is PLL cascading supported for Cyclone IV GX device transceivers?
Why does temperature dependent CDR lock loss happen on Cyclone V GT device receiver channels?
Are there any conditions where offset cancellation may fail on Stratix IV GX or GT devices?
Why can't I select the XAUI Hard PHY IP core for Arria V GX devices in Quartus II software version 12.0?
Are Arria II GX/GZ transceivers able to support 1.4V source on VCCH_GXB?
How can we assure that Stratix IV GX/GT and Arria II GX devices meet the PCI Express L0s to L0 transition time limit?
What are the valid pre-emphasis pre-tap settings for Stratix V GT channels?
Why can I not select ALT2GXB or ALTGX MegawWzard to instantiate high speed transceivers for Stratix GX devices in Quartus II 10.0 or later software versions?
Are there any known issues with Stratix V GX transceiver channel numbering in the Quartus II software versions 12.0, 12.0sp1, 12.0sp2 Chip Planner?
Are the default XAUI PHY IP transceiver PMA settings in Quartus II Software Version 10.1-SP1 and earlier capable of implementing a XAUI compliant link in Stratix IV GX and GT devices?
What is the read latency of an M20K ROM that must be accounted for when performing MIF-based streaming dynamic reconfiguration Stratix V GX devices?
Are there any known issues when selecting an Input REFCLK frequency in the Low Latency PHY for a Stratix V GT channel?
Error: Standard RX/TX PCS Parameter 'hd_pcs8g_digi_rx/tx_byte_deserializer' is set to an illegal value of 'en_bds/bs_by_2'. This mode is not supported with device speed grade of '8_H6', PMA WIDTH of 'twenty_bit' on atom.
Are there any known issues with dynamic reconfiguration and offset cancellation features in Stratix ® IV GX?
Why do I see an error in Modelsim when using the Stratix V CUSTOM_PHY IP automatic simulation script in Quartus II Software Version 10.1-SP1?
Are there different connection recommendations for VCCL_GXB on Arria II GX devices versus Arria II GZ devices?
How do I use an FPLL as a Tx PLL in Arria V GX and Stratix V GX devices?
What is the active word mapping of the Arria V GX Custom PHY when channel reconfiguration is selected?
Does VCCL_GXB need to be powered when transceivers are not being used in Arria V GX/GT devices?
Do Arria V GX devices support transceiver PMA Direct mode?
What power supplies are related to REFCLK buffers associated with high speed transceiver blocks in Stratix IV GX/GT devices?
Why does the Arria II GX transceiver CDR, configured in automatic locked mode, keeps the rx_freqlocked signal asserted in any other mode except PCIe mode?
How can I use the Stratix V GX transceiver Custom and Low Latency PHY IP components in Qsys?
How can I change the default transceiver VCCH and VCCA_L/R voltage settings for Stratix IV GX and Arria II GX devices?
How do I resolve setup and hold time violations for Stratix IV Transceivers in Basic (PMA Direct) mode if I use Quartus II software version 9.0SP2?
Error (11692): Design cannot be fitted into HSSI strip. 2 pma_aux_blocks under reference clocks set: dup_3ch_tx_pll_refclk[0]
Is the EyeQ feature supported on Stratix IV GX and GT engineering silicon devices?
Do Arria V GX devices support the Rate Match FIFO option when the word aligner is in manual alignment mode, and the PMA-PCS interface is 20 bits wide?
Why does Cyclone IV GX device EP4CGX30F484 does not support various protocols listed in the device handbook?
Can I dynamically switch between normal and reverse serial loopback transceiver modes in Stratix IV GX devices?
Are there any potential issues when releasing the receiver from reset when receiving a word alignment pattern on Altera transceiver devices?
How do I tell Quartus to use elevated voltages for Stratix V GX ES transceiver supplies VCCA_GXB, VCCR_GXB, VCCT_GXB and VCCH_GXB?
Are there any known issues with Stratix IV GX/GT device transceiver multi-PLL reconfiguration?
How should I control the rateswitch port in PCI Express (PIPE) x4 and x8 configurations for Stratix IV GX device?
Error: invalid command name "::alt_xcvr::ip_tcl::ip_module::ip_log_invalid_parameter"
Why do I get compilation error when I select clk [1] through [9] as the input clock source for the ATX_PLL in the MegaWizard?
Are there different RREF resistor requirements for Stratix V ES vs production devices?
Can I dynamically reconfigure a Stratix IV transceiver between Deterministic Latency mode and other functional mode?
Will I get a correct datarate when using dynamic reconfiguration to configure transceiver channels to listen to ATX or CMU PLLs driving the central clock divider in Stratix IV GX and GT devices when using Quartus II Software Version 10.0?
Why does my Arria V GZ Transceiver Toolkit design crash when using Quartus II software version 14.0?
Is the Adaptive Equalization feature supported on Stratix IV GX and GT engineering silicon devices?
Why does my PCI Express x1 Gen 1 design fail to fit on Arria II GX devices when using Quartus II Software Versions 10.0 and 10.0-SP1.
Is transceiver Tx PLL dynamic reconfiguration for Stratix V GX devices supported in Quartus II Software Version 11.1?
Warning (*): Ignored filter: sv_reconfig_pma_testbus_clk could not be matched with a clock
Are there any problems when selecting External PLL mode on the Native PHY Megawizard for Arria V GX and Stratix V GX devices?
Why is my Stratix IV GX/GT system exhibiting receiver bit errors when using dynamic reconfiguration to change between PCIe mode and any other transceiver mode?
Why do I see unexpected behavior on the rx_pll_locked outputs of the Stratix IV GX transceiver when the CDR is configured in Lock- to-Data (LTD) mode?
What is the active bit mapping of the Arria V GX Custom PHY configured to use the 8B10B block when channel reconfiguration is selected?
Why does the Stratix IV GX/GT transceiver CDR, configured in automatic locked mode, keep the rx_freqlocked signal asserted in any other mode except PCIe mode?
Why the DFE can’t find the optimal parameters sometimes?
Have there been any file name changes in the Stratix V transceiver Megawizard files in Quartus II 12.1?
When reconfiguring a transceiver channel to switch between CMU PLL within the transceiver block to an additional CMU PLL or ATX PLL outside the transceiver block in Stratix IV GX device, why does the transceiver block create incorrect tx_clkout frequency?
Why does the Quartus II software fail to fit more than four groups of 40G BaseKR IP into one side of a Stratix V device?
Why does Quartus II 9.1 gives a Fitter error when I try to fit four separate instances of the same ALTGX Megawizard generated module/entity in the same transceiver block of a Stratix IV GX device?
How do I enable the Stratix® IV GX device to pass the PCI Express Electrical Gold test requirements on the v2.0 Compliance Base Board (CBB)?
How do I identify if my Stratix IV GX device has the capability of configuring the CMU Channel as a transceiver channel?
Why does Quartus II software version 15.0 and earlier allow an unsupported registered phase compensation FIFO setting for channels 1 and 2 of Arria V device transceiver banks GXB_L0 and GXB_R0?
Is there a problem with dynamic reconfiguration for a receiver only channel in Stratix IV GX/GT devices?
Error (175020): Illegal constraint of pin <pin name> to the region <location> to <location>: no valid locations in region
What are the changes required for Basic (PMA Direct) mode configuration in Stratix IV Transceivers if I use Quartus II software version 9.0SP1?
Why is my rx_signaldetect output signal always HIGH even when there is no serial data input at my receiver?
Error (169032): I/O bank QL&lt;n&gt; contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank
Will the Stratix V Native PHY IP PMA direct mode support signal detect?
Why does the Transceiver Reconfiguration Controller's reconfig_busy output get stuck high after a reset?
Are there any known problems with tx_digitalreset in Stratix V GX?
Can Altera GX/GT/GZ device high speed transceivers handle Spread Spectrum Clocking (SSC), as required by PCIe or SATA/SAS protocols?
Why do I get compilation error when I select clk [1] through [9] as the input clock source for the ATX_PLL in the MegaWizard?
Are there any known problems when trying to simulate the Quartus II software versions 12.1, or 12.1sp1 Altera 10GBASE-KR PHY IP in Cadence ncsim?
Why do I see the following error "AutoSweepControllerPMAAnalog constructor failure" in the Stratix V GX and Arria V GX transceiver toolkits when running the AutoSweep function?
Are there any known issues with the transceiver Tx signal integrity that may increase the BER on Stratix V GX production silicon devices?
Are there any known issues with the Stratix V Low Latency PHY when using an embedded reset controller in Quartus II software version 12.0?
Can I connect unused GXB_REFCLK pins directly to GND in Cyclone® V GX devices?
Internal Error: Sub-system: HSSI, File: /quartus/periph/hssi/hssi_reconfig_op.cpp, Line: 5331
Why cannot I enable 64B/66B block in Intel® Stratix® 10 L-tile or H-tile Native-PHY at 25.78125Gbps speed ?
Are there any issues when launching the Auto Sweep and/or EyeQ function from the Receiver Link tab of the Transceiver Toolkit for Stratix V GX devices?
Error (178004): Could not find location for Clock Divider <instance name> that enable routing of bonding clock lines
Why does the rx_seriallpbken port not appear when I select serial loopback on an ALTGX Megawizard Plugin Manager for Cyclone IV GX devices?
Why does the Fitter report show an incorrect "OCT_100ohms" receiver termination when external termination is used for Cyclone IV devices with Quartus II software versions 15.0 and earlier?
Can Stratix® GX and Stratix II GX transceivers drive/receive high speed signals over long copper cables e.g. Cat5e, Cat6, etc?
Is there any issue associated with the waitrequest signal during Stratix V GX transceiver MIF reconfiguration?
Why doesn't tx_forceelecidle has any affect on the transmitter output in simulation for Cyclone IV GX devices?
Why does the rx_freqlocked signal get stuck high for an Rx only transceiver instances in Cyclone® IV GX devices?
Are there incorrect Transmitter (CMU) PLL bandwidth settings when ALT2GXB is configured in “Transmitter Only” mode
If I have multiple instantiations of the same ALT2GXB module/entity, can I change PMA (Vod, Pre-emphasis and Equalizer) settings in one of these instances?
What is the minimum peak-to-peak differential input voltage for Cyclone IV GX transceiver input reference clock?
Why can’t I run RTL simulations of Intel Stratix 10 device fPLL VHDL models using Cadence Xcelium tools?
How do I enable Intel Arria 10, Cyclone 10, and Stratix 10 device Transceiver Toolkit capability in the Native PHY IP?
Why did the Fitter Error Reported When Using PCIE HIP Channels for PIPE Design
HardCopy IV GX timing model data corrected
Has there been an update to the Arria 10 Soft DFE IP for PCIe Gen3?
Quartus® II software fitter error: "GXB REFCLK divider could not be added after signal "rx_cruclk[0]" because it feeds cruclk port of GXB Receiver channel alt2gxb:alt2gxb_component\| channel_rec[0].receive" that uses channel interface or channel internals reconfiguration"
How can I implement manual word alignment in my Stratix II GX transceiver design if this option has been grayed out in alt2gxb Megawizard?
How do I set 6dB equalizer DC gain in ALT2GXB MegaWizard?
What is the mapping between the signal detect threshold voltage (Vth) and the setting in the Stratix IV GX ALTGX megawizard?
Why does rx_freqlocked signal get stuck low, even though the tx_clkout and rx_clkout are successfully reconfigured, after Channel Reconfiguration in Cyclone IV GX devices?
Is the alignment pattern set correctly when using the ALT2GXB Megawizard in Quratus II Software Version 9.1 SP2 in Stratix II GX devices?
The Quartus® II compiler fails for Stratix II GX designs with transceivers configured in bonded x4 (PCI Express (PIPE) x4, XAUI and Basic x4) and bonded x8 (PCI Express (PIPE) x8) configurations depending on channel placement. Are there any channel placement constraints in these configurations? Is there any recommendation for lane mapping between the Stratix II GX transceiver physical channels to the PCI Express edge connector?
Why do I see unexpected behavior in the transceiver when I dynamically reconfigure the Stratix® II GX transceiver analog controls?
Are there any problems with channel 3 of a transceiver block after dynamic reconfiguration in Cyclone IV GX devices using Quartus II Software Version 10.1SP1 and earlier?
What is the correct data rate range for VCCH_GXB = 1.5V in Stratix IV GX devices?
Why is offset cancellation triggered every time the reconfig_reset signal is asserted in Cyclone IV GX devices?
Why does my Quartus II software version 8.1 .pin file differ from the Quartus II software version 9.0 pin file for my Stratix IV GX device design?
What is the simulation behavior for rx_phase_comp_fifo_error when there is a difference between the read and write clock frequencies in Cyclone IV GX devices?
Why is the rx_phase_comp_fifo_error output port of the Stratix IV GX transceiver always at an undefined state during functional simulation?
Can the Stratix II GX transceiver Word Aligner be bypassed ?
What is the difference between the Stratix IV GX devices in the -2 and -2X speed grades?
Critical Warning: GXB Central Management Unit (CMU) &lt;Instance specific to your design&gt; is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be
Why doesn’t the ALTGX receiver work correctly when configured for serial loopback or reverse serial loopback modes using MIF based dynamic reconfiguration for Cyclone IV GX devices in Quartus II Software Version 10.0 and 10.0-SP1?
Why does Quartus II software not support 10GBASE-R, as stated in Stratix V device handbook?
Error (178018): Channels in the bonded channel groups containing the following must be placed in contiguous locations. If CMU PLLs are used, gaps must be left for the transmit PLL channel.
Is the SerialRapid IO protocol supported for Cyclone IV GX transceivers in F324 and smaller packages?
Do Cyclone IV GX devices support single-ended reference clock support in IO Bank 3B and 8B?
Is there a combination of VCCHTX and Vcm in Stratix® II GX that can be used across the entire range of operation?
What is the supported GXB_VCCL, GXB_VCCT and GXB_VCCR voltage for Arria V GX devices at datarates > 3.2 Gbps?
Can I use the programmable differential on-chip termination (OCT) 85-Ω setting in Cyclone IV GX devices?
Can I use the reset sequence recommended by Altera® for PIPE mode also?
Why can't I select 2.5v for VCCA_L/R on Stratix IV GX devices when using an ATX PLL?
Why does VCCH remains at 1.5V even if I it to set 1.2V, when using the Serial RapidIO Megacore in Quartus II 8.0?
Do I need a license to use the XAUI Hard IP in Stratix IV GX/GT devices?
Why does the word aligner not work correctly with the synchronization state machine when I check “Enable word aligner output reverse bit ordering” option in Stratix II GX ALT2GXB MegaWizard?
Why Programmable PPM Detector options of +/-500 PPM and +/-1000 PPM in ALTGX Megawizard is not supported in Cyclone IV GX device?
Are there any problems when performing dynamic reconfiguration of Arria V GZ and Stratix V device non-PCI Express channels when PCI Express CvP is enabled in Quartus II software version 13.1?
Is the transceiver EyeQ function supported on Arria II GX devices?
Why is rx_freqlocked stuck low after channel reconfiguration when using multiple reconfiguration controllers in Cyclone IV GX devices?
What will happen if unused Stratix II GX transceiver pins are floating?
Do I need a calibration clock in Stratix® II GX devices when I have external termination?
AN 558: Implementing Dynamic Reconfiguration in Arria II Devices: Known Issues
Why is my Arria II GX system exhibiting receiver bit errors when using dynamic reconfiguration to change between PCIe mode and any other transceiver mode?
Are there any problems if a floating voltage exists on the VCCH_GXB supply rail before it is ramped in Cyclone IV GX devices?
Why does TimeQuest Timing Analyzer in Quartus II software versions 7.1 SP1 and beyond report several of the reset and serial loopback ports on high speed transceivers on Stratix II GX devices as unconstrained paths in red?
What is the behavior of the byte ordering block when I enable two-symbol byte ordering option in basic double-width mode of the ALTGX Megawizard interface for the Stratix IV GX device?
Are there any restrictions for which reference clock source should be used for the CMU PLL on Arria V GT devices when running at data rates > 6.5536Gbps?
Is it acceptable to connect multiple unused Stratix II GX positive and negative transceiver signals of the same type through single 10K Ohm pull-up or pull down resistors respectively?
Where can I find dynamic reconfiguration channel interface details for Arria II GZ devices?
Why does the 'rx_dataout' of Stratix® II GX transceiver channel stuck at a fixed value under some conditions
Why does the rx_byteorderalignstatus output port not get asserted on the first occurrence of the byte ordering pattern in Basic double-width configuration in Stratix IV GX device?
Why does the Quartus® II software .pin file report that the transceiver VCCR_GXB supply needs 1.2v on Arria® V GX -C4, -C5, -I3 and -I5 devices for datarates >3.2Gbps?
Does Altera ALTGX PHY allows lane reversal for a XAUI link (lane 0 to lane 3, lane 1 to lane 2, and so on)?
Error (177013): Cannot route from source HSSI reference clock divider output to the Receiver channel because the destination is in the wrong region
Do Cyclone IV GX devices support 1.4V PCML I/O standard?
Why do I get this rx_out_wire[n] related warning for my Arria GX high speed transceivers: “The following nodes have both tri-state and non-tri-state drivers”?
Error : Device has stopped receiving configuration data Error message received from device : Device is in configuration state Operation failed
Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Why is the minimum transceiver refclk frequency for fPLL allowed in Quartus is 50MHz although datasheet shows minimum value of 25MHz?
Why I cannot access PCIe registers after generating Quartus Prime 16.1 PCIe CvP mode?
What transceiver PMA blocks are included in the Intel® Arria® 10 device internal serial loopback path?
Why is rx_signaldetect always stuck high in hardware and stuck low in simulation for Arria II GX devices?
Why does the SerialLite II IP Core show incorrect device in Project Navigator for Arria® II GX family?
Why I cannot read back the same Vod and Equalization values in simulation that I selected in ALTGX Megawizard settings or programmed through dynamic reconfiguration?
Why does the TSE signal rx_recovclkout or Native PHY signal rx_pma_clkout not toggle in Cyclone V
Why do I see occasional temperature dependent bit errors on Cyclone IV GX Rx transceiver channels using Quartus II software version 12.0SP1 and earlier?
Error: Could not find location for HSSI PMA RX Buffer that satisifes the VCCR_GXB/VCCT_GXB Voltage requirement of 1_1_V (1 location affected)
Why do I get the error message “Error: Parameter "termination" of instance "receive_pma0" has illegal value "OCT 100 Ohms" assigned to it. Possible parameter values are: "OCT 150 OHMS", "OCT 85 OHMS", "OFF".” for Cyclone IV GX devices?
Why can't I generate transceiver MIF files for Arria V GX B3 Production devices in Quartus II software version 12.0sp2?
Should I use AC or DC coupling when implementing the SerialLite II Protocol?
What is pll_areset connected to in the ALTGX megafunction for Cyclone IV GX devices in Quartus II software version 10.0 and 10.0sp1?
Why do I get an Error message when I try to compile my transceiver application design running at &#8805; 2.97Gbps data rate in the Quartus II software versions 10.1 or 10.1 SP1?
Why is the input common mode voltage (VICM) of the Arria II GX dedicated transceiver refclk pins lower than the 1.1V device specification?
Why cant I use the Transceiver Toolkit EyeQ feature with Arria V GZ devices?
How do I disable the transceiver On-Chip-Termination (OCT) of the Stratix IV GT, 10GBase-R PHY IP?
Why is the PCIe Gen2 link for Arria II GZ transceivers not getting established?
What are the connection guidelines for the REFCLK pin (GXBR4F) in the Arria 10 10AX115NF40 package?
Why do I get a syntax error related to "Missing or invalid file version" when I try to open Stratix IV GX device Eldo models in Hyperlynx tool?
Why does Receiver Bitslip not work in Low Latency PHY IP for Stratix V GX devices?
Why does my Stratix V GX ES Device, Native PHY design show the following error: 10G RX PCS param 'hd_pcs10g_rx_chnl_frmsync_mfrm_length' set to illegal 'mfrm_user_length'?
What is the value of the transceiver differential Rx On-Chip Termination (OCT) on Arria II GX devices?
If I am using the top ATX PLL in the bank and the ATX PLL supports the data rate for Stratix® V, can I ignore Critical Warning for ATX PLL Range?
How do I know which column of the Pin-Out File to use for the Stratix IV GX device when I am in the F1152 package?
Why doesn't the 10GBase-R PHY IP obtain block lock when the "Use external PMA control and Reconfig" option is enabled in Stratix IV GT devices?
Why does the transceiver pll_locked signal deassert when rx_analogreset is asserted during simulation of Cyclone IV GX devices?
Why are VCC_CLKIN power supplies for transceiver REFCLK required to be connected to 1.5V source as reported in Quartus II Fitter Report?
Are there any issues when performing dynamic reconfiguration using a mix of RX only and duplex channels in Cyclone V GX devices?
What is the status of the transceiver Tx pin during device configuration and when entering user-mode on Stratix V GX devices?
How do I change the transmitter slew rate of a transceiver in Stratix IV GX devices?
What will be my default analog settings (pre-emphasis, equalization, Vod) for GX high speed transceivers, when dynamically reconfiguring GX transceivers from one mode to another?
How should I connect the MIF address bus between the reconfiguration controller and MIF ROM when word addressing is used in Stratix V GX devices?
Why is the rx_freqlocked signal stuck in deasserted state after Cyclone IV GX transceiver PLL reconfiguration? What are the correct steps for Cyclone IV GX transceiver PLL reconfiguration?
Error (12252): Alt_xcvr_reconfig_cpu: "Device family" (deviceFamily) (Stratix V) out of range. Valid ranges: [Cyclone III:Cyclone III, Cyclone III LS:Cyclone III LS, Cyclone V:Cyclone V, Unknown:Unknown]
How are XAUI and PCIe x4 (bonded channels) lane assignments made in Quartus II software?
When I simulate the PCI Express (PIPE) x8 configuration in Stratix IV GX device, why is the coreclkout [1] port always at logic low?
Why there is error when simulating DXAUI with modelsim?
Why does the XCVR_REFCLK_PIN_TERMINATION, DC_COUPLING_INTERNAL_100_OHM assignment fail in Quartus® software version 12.0?
Are there any problems if a floating voltage exists on the VCCL_GXB supply before it is ramped up on Cyclone IV GX devices?
Error: set_port_property sets an illegal FRAGMENT_LIST for port unused_rx_parallel_data
How do I disable the transceiver On-Chip-Termination (OCT) of the Stratix IV GT device 10GBase-R PHY IP?
Why does Quartus II 10GBASE-R PHY MegaCore not allow me to pick any of the pre-emphasis, Vod or DC gain values from the full range described in the device handbook?
Error (12252): Alt_xcvr_reconfig_cpu: "Device family" (deviceFamily) (Stratix V) out of range. Valid ranges: [Arria V:Arria V, Unknown:Unknown]
Why won't my Arria V GX bonded transceiver instance fit in Banks GXB_R0 and GXB_R1?
How do I decouple shared supply rails with very different noise, current, transient, and Feffective specifications?
What are the supported minimum and maximum effective data rate limits for basic single-width and double-width configurations supported by the ALTGX Megawizard for Stratix IV GX device?
Which Stratix IV GX device do I target in Quartus II software if I have ordered the EP4SGX230FF35C2NES part?
Why is the rx_patterndetect port width two bits instead of one for a 16-Bit PMA-PCS Interface in Arria II GX devices?
Why can't I connect the transceiver reconfig_to/from_xcvr ports between the Reconfiguration Controller and the 1G/10GbE and 10GBASE-KR PHY IP in QSYS on Stratix V GX devices using Quartus II software versions 12.1 and earlier?
Why does rx_freqlocked signal get stuck high when there is no data or rx_signaldetect toggles when data is present on Cyclone IV GX devices?
Do Stratix IV GX devices support PCIe Gen2 x1/x4/x8 in C4 and I4 speed grades?
How do I disable the scrambler in the Intel® Stratix® 10 PCIe* Hard IP ?
Why do i get Warning (16817): Verilog HDL warning at alt_etipc3_nphy_elane.v (12698)
Why do I see “Couldn't grab settings for channel TX/RX/LINK\|*“ in the Intel® Transceiver Toolkit when I have multiple tiles used in my Stratix® 10 design?
Why am I not able to configure the ALT2GXB instance in the MegaWizard in Parallel Loop-back running BIST under 3.125 Gbps?
Warning (10034): Output port "error" at XCVR_reconfig.v(375) has no driver
What is the proper layout for RREFB pins in Stratix GX devices?
Why is the Stratix® GX jitter spec in the datasheet not given for all data rates?
Why doesn't the generic transceiver Tx and Rx polarity inversion feature work on Stratix V, Arria V, Cyclone V devices with Quartus II Software versions 12.1sp1 and earlier?
Error: native_10g_fechp_322_inst: The current value "continuous" for parameter "DFE adaptation mode" (rx_pma_dfe_adaptation_mode) is invalid. Possible valid values are: "".
Is there a known issue with Stratix 10 3V IOs during configuration ?
Is there a known issue with Stratix 10 3V IOs in user mode ?
How do I add Intel Stratix® 10 L-Tile and H-Tile device transceiver PMA assignments to my QSF file?
Are there any problems in the VHDL valiant of 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core?
Why do I see r_r2 in the Quartus fitter reoport of Rapid IO XCVR RX On-Chip ternaminaton?
Why does the Stratix 10 Native PHY IP Core for PIPE lane polarity inversion not take effect immediately?
Error(15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Critical Warning(18234): ATX PLLs <hierarchy>:xcvr_atx_pll_a10_0\|a10_xcvr_atx_pll_inst\|twentynm_atx_pll_inst and <hierarchy>:xcvr_atx_pll_a10_0\|a10_xcvr_atx_pll_inst\|twentynm_atx_pll_inst are <number> ATX PLLs apart. For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 5 ATX PLLs apart.
Why is app_int_ack status signal not available for PCI Express Hard IP Core of Cyclone V devices
What slew rate control of the TX output signal of Intel Stratix10 L-tile and H-tile device transceiver should I use when disabling “Use default TX PMA analog settings” ?
Why do I see a Bit Error Rate (BER) of 1 after drawing an eye in the Intel® Transceiver Toolkit when using Intel Stratix® 10 E-Tile transceivers?
Why does the Intel FPGA Advanced Link Analyser Tool hang or take a long time to run a simulation?
Info: MyPHY.xcvr_atx_pll_s10_htile_0: The current value "GX clock output buffer" for parameter "Primary PLL clock output buffer" (primary_pll_buffer) is invalid
Why isn't Arria 10 Transceiver calibration completed?
Error(18969): IO Banks < 1C 1D 1E 1F > are within same HSSI strip, Transceivers and PLLs placed inside these IO Banks needs to use the same power supply voltage. Transceivers and PLLs are using 1030 mv 1120 mv power supplies.
Why cant I run the Transceiver Toolkit Auto sweep feature for VOD values of lower than 6 in the Quartus II Software, versions 12.0 and later?
Why do I get a compilation error related to Starting Channel Number 68, when I implement AN 571, SFI-5.1 design?
What are the PRBS7, PRBS15, PRBS23, and PRBS31 polynomials used in the Altera Transceiver Toolkit?
How should you connect power, ground (gnd), and input signals on unused High Speed Serial Interface (HSSI) Transceivers (XCVR)s?
How do you set up the Channel Loopback Modes for the Stratix GX family?
How should unused REFCLKB, GXB_RX, and GXB_TX pins be connected in Stratix GX devices?
Can I use the “Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE” option in the Intel® Stratix® 10 E-Tile device Native PHY IP?
What transceiver PMA settings should I use when disabling the “Use default TX PMA analog settings” and “Use default RX PMA analog settings” in the Intel Stratix 10 L-Tile or H-Tile device Native PHY IP?
Why is the valid transmitter output differential voltage (Tx Vod) settings against pre-emphasis settings described in Arria 10 Transceiver Phy User Guide different compared to "Arria_10_Pre_Emphasis_and_Output_Swing_Settings.xlsx" excell sheet?
Why is the transmitter voltage, VCCT_GXB described in Arria 10 Transceiver Phy User Guide for QSF assignment different compared to value in Arria 10 datasheet?
Why doesn’t reverse serial loopback work on transceiver channels configured in GXT mode on Intel® Stratix® 10 devices?
Why might I see a poor Bit Error Rate (BER) after performing dynamic reconfiguration of the Native PHY IP using the embedded streamer of a Stratix® 10 E-Tile device in Quartus® software version 18.0?
Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation hang in the reset state?
Why will packet loss be seen in Stratix 10 L/H tile 10G RX interface
What is the meaning of the SerialLite II Deskew Tolerance in Table 3-1 of the SerialLite II IP Core User Guide (PDF)?
Why do I see high BER when using Intel® Arria® 10 transceivers in RX simplex mode?
Error (10476): VHDL error at <ip_instance_name>.vhd(88): type of identifier "fboutclk" does not agree with its usage as "std_ulogic" type
Why does Intel® Arria® 10 ATX/PMA calibration fail when 'pin_perstn' of PCIe HIP keeps asserted in Intel Quartus® Prime 16.1 or before?
Is there any error with Stratix® 10 L- and H-Tile Standard PCS data rate support in user guide
If the Intel® Stratix®10 L- or H-Tile device has used transceiver channels not plugged in (example, chip to optical module interface), would the performance degrade?
To save power when the transceiver channels are not in used, can I keep the transceiver channels in the Intel® Stratix®10 L- or H-Tile design in reset ?
If the Intel® Stratix®10 L- or H-Tile device is left in power up but not configured state, would the unused transceiver channels be subjected to performance degradation?
When using a simplex RX or TX channel in the Intel® Stratix®10 L- or H-Tile device, do I need to assign the preserve unused channel QSF to the unused RX/TX of the simplex channel?
why do PMA registers of any other channels might get corrupted when user re-calibration or background calibration process of a channel is happening?
How do I merge simplex transceiver PHYs inside Intel® Quartus® Prime Platform Designer when using Intel Arria® 10 and Intel Stratix® 10 L-Tile/H-Tile devices?
Why does the bandwidth setting not change when using the fPLL Intel Arria 10 FPGA IP in SDI_Direct mode?
What are the Intel® Stratix® 10 E-Tile Native PHY IP Core Initial Adaptation Effort Levels?
Why does the Intel® Stratix® 10 E-tile Native PHY transceiver channel’s MIF streamer status bit not pulse or transmit/receive at the new datarate when I load in a new configuration profile?
Why is my simplex A10 Native PHY IP generating duplex-related reconfiguration files?
What are the expected behavior of CDR automatic lock mode and manual lock mode ?
What is the data rate for preset GIGE-1.25 Gbps and GIGE-2.5 Gbps options in the Custom PHY IP Core?
Why do unused transceiver channels in my Intel® Stratix®10 L- or H-Tile devices degrade over time?
How to add the per-pin assignment to preserve unused transceiver channels?
Why does the “RX Word Aligner Pattern (Hex)” value appear incorrectly for the GbE or GbE 1588 Transceiver configuration rules of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY?
Can I use the Internal Oscillator setting of the Configuration Clock Source field for transceiver calibration on Intel® Stratix® 10 L-Tile and H-Tile devices?
Why does the "rx_10g_frame_mfrm_err" flag assert during an Interlaken non-framing layer control work when using Native PHY w/Interlaken preset?
How do I reduce the number of “informational” simulation messages emitted by the Intel® Stratix® 10 transceiver models?
Can I perform back to back writes to the Intel Stratix 10 and Agilex E-Tile Native PHY RS-FEC registers?
How do I simulate transceiver REFCLK behaviour for Intel® Arria® 10 and Intel Stratix® 10 L/H-Tile devices?
Error: native_phy_ip.xcvr_native_s10_htile_0: The current value "8" for parameter "CTLE AC Gain" (rx_ctle_ac_gain) is invalid. Possible valid values are: "4"
Why might the PCI Express configuration fail link training at low temperature for Cyclone V GT and ST devices?
Are there any problems simulating the ATX PLL Reconfiguration profile feature using Arria 10 devices?
Are tx_polinv and rx_polinv ports available for Enhanced PCS of Transceiver Native PHY for Arria 10 and Cyclone 10 devices?
Why there isn’t any PLL usage if I compile the project with Stratix® 10 E-tile transceiver channels by Intel® Quartus® Prime Pro Edition software version 19.3 and earlier?
The software design constraints (SDC) provided by the 10GBASE-R IP is invalid when the IP is instantiated within the VHDL generate block.