Transceiver PHY IP – Support Center

Welcome to the Transceiver PHY IP support center! 

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.  

Enjoy your journey!

Get support resources for Intel® Stratix® 10Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation ArchiveTraining CoursesVideos and WebcastsDesign Examples, and Knowledge Base.

Table 1 - Device Variant and Feature Support

Device

Intel® Cyclone® 10

Intel® Arria® 10

Intel® Stratix® 10

Device Variant

GX

SX(3)

GX(3)

GT(4)

GX/SX L-Tile

GX/SX H-Tile

Maximum Data Rate
(Chip-to-Chip)(1)(7)

GX Channels

12.5 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

GXT Channels

N/A

N/A

25.8 Gbps

26.6 Gbps

28.3 Gbps

Maximum Data Rate
(Backplane)(8)

GX Channels

6.6Gbps

12.5 Gbps

12.5 Gbps

12.5 Gbps

28.3 Gbps

GXT Channels

N/A

N/A

Maximum Channels per device

GX Channels

12

96

72

96

96

GXT Channels

N/A

N/A

6

32

64

Hard IP

One PCIe Gen2 x4 per device.

PCIe* Gen3 x8 up to 4 per device

PCIe Gen3 x16 up to 4 per device

50/100 Gbps Ethernet MAC up to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) (6)

SR-IOV support is not available.

  1. The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel® Arria® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel® Arria® 10 Device Datasheet.
  2. Intel® Arria® 10 and Intel® Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  3. For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications.
  4. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications.
  5. Intel® Stratix® 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel® Stratix® 10 L-/H-Tile Transceiver PHY User Guide.
  6. SR-IOV stands for Single-Root Input Output Virtualization.
  7. Intel® Arria® 10 and Intel® Stratix® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  8. Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.

Use the E-Tile Channel Placement Tool in conjunction with the Intel® Stratix® 10 GX, MX, TX, and SX Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software.The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs

 

The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.
 
Models
Title Description
Intel® Arria® 10 Device Configuration of a Simplex Transceiver Watch this video to learn how to place an Intel® Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.
Dynamic Reconfiguration of an Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel® Arria® 10 devices.
How to Use the Transceiver Toolkit Part 1 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.
How to Use the Transceiver Toolkit Part 2 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 3 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 4 Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
Intel® Arria® 10 Transceivers: Pre-Emphasis Basics Learn the basics of the Intel® Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.
Performing Dynamic Reconfiguration for the Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel® Arria® 10 devices.
Reconfigure Intel® Arria®10 Device Transceivers Using Embedded Streamer Watch this video to learn  how to perform dynamic reconfiguration with the Intel® Arria® 10 device transceiver Standard PCS using the embedded streamer.
Use the IBIS-AMI Model to Estimate Signal Integrity of Intel® Arria® 10 Device Transceiver Watch this video to learn how to perform a signal integrity simulation with the Intel® Arria® 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.

Intel® Stratix® 10 Device L-Tile/H-Tile Transceiver PHY Debug Tool

This debug tool consists of four sub-tools
1) Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
2) Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS  generator/checker status
3) Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
4) Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel® Stratix® 10 Device L-Tile/H-Tile

Intel® Arria® 10 Device Transceiver PHY Debug Tool

This debug tool consists of the same four sub-tools as the Stratix® 10  version:
1) Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
2) Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS  generator/checker status
3) Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
4) Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel® Arria® 10 Device 

Intel® Quartus® Prime Design Suite Release Notes (note: Transceiver Native PHY IP Release Notes are now found within Intel® Quartus® Prime Design Suite Release Notes)

Refer to the chapter on Debug Functions in the following user guides:

Intel® Cyclone® 10 Devices

Intel® Arria® 10 Devices

Intel® Stratix® 10 Devices

Other Technologies