Transceiver PHY IP – Support Center

Welcome to the Transceiver PHY IP support center!

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Training Course Videos, Webcasts Design Examples, and Knowledge Base.

What's New

Intel® Agilex™ Device Datasheet

E-Tile Transceiver PHY User Guide

AN 886: Intel® Agilex™ Device Design Guidelines

Which Intel® FPGA Device Family Should I Use?

Device		Intel® Cyclone® 10	Intel® Arria® 10			Intel® Stratix® 10			Intel® Agilex™
Table 1 - Device Variant and Feature Support
Device Variant		GX	SX⁽³⁾	GX⁽³⁾	GT⁽⁴⁾	GX/SX L-Tile	GX/SX H-Tile	MX/TX E-Tile	AGF E-Tile
Maximum Data Rate (Chip-to-Chip)⁽¹⁾⁽⁷⁾	GX Channels	12.5 Gbps	17.4 Gbps		17.4 Gbps	17.4 Gbps	17.4 Gbps	N/A	N/A
	GXT Channels	N/A	N/A		25.8 Gbps	26.6 Gbps	28.3 Gbps	28.3 Gbps	N/A
	GXE Channels	N/A	N/A		N/A	N/A	N/A	28.9 Gbps (NRZ) 57.8 Gbps (PAM4)	28.9 Gbps (NRZ) 57.8 Gbps (PAM4)
Maximum Data Rate (Backplane)⁽⁸⁾	GX Channels	6.6Gbps	12.5 Gbps		12.5 Gbps	12.5 Gbps	28.3 Gbps	28.3 Gbps	N/A
	GXT Channels	N/A	N/A		12.5 Gbps	12.5 Gbps	28.3 Gbps	28.3 Gbps	N/A
	GXE Channels	N/A	N/A		N/A	N/A	N/A	28.9 Gbps (NRZ) 57.8 Gbps (PAM4)	28.9 Gbps (NRZ) 57.8 Gbps (PAM4)
Maximum Channels per device	GX Channels	12	96		72	96	96	N/A	N/A
	GXT Channels	N/A	N/A		6	32	64	24	N/A
	GXE Channels	N/A	N/A		N/A	N/A	N/A	120	24 (and 32 P-Tile)
Hard IP		One PCIe Gen2 x4 per device.	PCIe* Gen3 x8 up to 4 per device			PCIe Gen3 x16 up to 4 per device	50/100 Gbps Ethernet MAC up to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) ⁽⁶⁾	10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514)	10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514)
Hard IP		SR-IOV support is not available.	PCIe* Gen3 x8 up to 4 per device			PCIe Gen3 x16 up to 4 per device

The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel^® Arria^® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel^® Arria^® 10 Device Datasheet.
Intel^® Arria^® 10 and Intel^® Stratix^® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications.
For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications.
Intel^® Stratix^® 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel^® Stratix^® 10 L-/H-Tile Transceiver PHY User Guide.
SR-IOV stands for Single-Root Input Output Virtualization.
Intel^® Arria^® 10 and Intel^® Stratix^® 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.

Intel® FPGA Device Datasheets

Additional Resources

Refer to the Overview chapter of the following user guides:

Intel® Agilex™ Devices

E-Tile Transceiver PHY User Guide

Intel® Stratix® 10 Devices

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 Transceiver PHY User Guide

Intel® Arria® 10 Devices

Intel® Arria® 10 Transceiver PHY User Guide

Where Can I Find Information on Transceiver Usage?

Use the E-Tile Channel Placement Tool in conjunction with the Intel® Stratix® 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software.The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs.

What Design Recommendations Should I Consider?

Intel® Agilex™ Devices

AN 886: Intel® Agilex™ Device Design Guidelines

Intel® Stratix® 10 Devices

Intel® Stratix® 10 Device Design Guidelines

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Device Errata and Design Guidelines

Intel® Arria® 10 Devices

Where Can I Find Information on Transceiver PHY IP Integration?

Intel® Agilex™ Devices

Intel® Stratix® 10 Devices

Intel® Cyclone® 10 Devices

Intel® Arria® 10 Devices

Where Can I Find Information on the Transceiver PHY IP Register Mapping?

Intel® Stratix® 10 Devices

Logical View of the Intel® Stratix® 10 L- and H-Tile Transceiver Registers

Intel® Cyclone® 10 Devices

Logical View of the Intel® Cyclone® 10 Transceiver Registers

Intel® Arria® 10 Devices

Logical View of the Intel® Arria® 10 Transceiver Registers

Analog Settings Guidelines

Intel® Stratix® 10 Devices

Intel® Stratix® 10 L-Tile/H-Tile Pre-emphasis and Output Swing Estimator

Intel® Cyclone® 10 and Intel® Arria® 10 Devices

Intel® Cyclone® 10 and Arria® 10 Pre-emphasis and Output Swing Estimator

Additional Resources

Intel® Arria® 10 Transceiver PHY Pin Planning (FPGA Wiki

Board Design Guidelines

Pin Connection Guidelines

Intel® Agilex™ Devices

Intel® Agilex™ Device Family Pin Connection Guidelines

Intel® Stratix® 10 Devices

Intel® Stratix® 10 Device Family Pin Connection Guidelines

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

Intel® Arria® 10 Devices

Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Schematic Review

Intel® Agilex™ Devices

Intel® Agilex™ Schematic Review Worksheet

Intel® Stratix® 10 Devices

Intel® Stratix® 10 GX, MX, and SX Schematic Review Worksheet

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 GX Schematic Review Worksheet

Intel® Arria® 10 Devices

Intel® Arria® 10 GX, GT, and SX Schematic Review Worksheet

Power Management

Simulation Models & Tools

Intel ® Advanced Link Analyzer

The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.

Models

Development Kit User Guides

Intel® Agilex™ Devices

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Applications

Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide

AN 835: PAM4 Signaling Fundamentals

AN 846: Intel® Stratix® 10 Forward Error Correction

Models

IEEE 1149.6 BSDL Files

Design Examples and Reference Designs

Intel® Stratix® 10 Devices

Intel® Cyclone® 10 Devices

Intel® Cyclone® 10 Transceiver PHY Basic Design Examples (Intel Communitites)

Intel® Arria® 10 Devices

Recommended Training Courses

Title	Type	Description
Building Interfaces with Arria® 10 High-Speed Transceivers	Instructor-Led	Learn the architecture of Intel® Arria 10 and Intel Cyclone® 10 FPGA transceivers and then the flow for incorporating them into an FPGA design.
Transceiver Basics for 20 nm and 28 nm Devices	Online	Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols.
Stratix® 10 Transceiver Basics	Online	Learn the basic building blocks that are found in Intel Stratix® 10 FPGA transceivers used to support a range of high-speed protocols.
Transceiver Toolkit for Arria® 10 Devices	Online	Learn how to debug and dynamically fine tune the analog settings of your Intel® Arria® 10 and Intel® Cyclone® 10 FPGA transceivers.
Advanced Signal Conditioning for Arria® 10 FPGA Transceivers	Online	Learn the analog capabilities of Intel® Arria® 10 FPGA transceivers and how to use them to improve link performance.
Building a Generation 10 Transceiver PHY Layer	Online	Learn how to build a custom transceiver implementation using the Intel® Arria® 10 and Intel® Cyclone® 10 FPGA transceiver IP blocks.
Building an Intel® Stratix® 10 FPGA Transceiver PHY Layer	Online	Learn how to define the three resources that make up an Intel® Stratix® 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller.
Generation 10 Transceiver Clocking	Online	Learn the clocking resources that are found in Intel Arria® 10 and Intel® Cyclone® 10 FPGA transceiver blocks.

Other Training Courses

Transceiver Training Courses

Title	Description
How to Dynamically Reconfigure PMA Analog Parameters for Intel® Cyclone® 10 GX	Learn the implementation of Intel® Cyclone® 10 GX FPGA Native PHY PMA analog parameters using direct reconfiguration flow.
How to Perform the Intel® Cyclone® 10 GX Dynamic Reconfiguration with fPLL Switching and Channel Reconfiguration Using Direct Write Method	Learn how to perform the transceiver dynamic reconfiguration functional simulation with Intel® Cyclone® 10 GX FPGA fractional phase-locked loop (PLL) switching and channel reconfiguration using the direct write method.
How to Perform Intel® Cyclone® 10 GX Native PHY ATX PLL Switching and Channel Reconfiguration	Learn how to perform the functional simulation with Intel® Cyclone® 10 GX FPGA Native PHY ATX PLL switching, channel reconfiguration with embedded streamer, and channel recalibration.
How to Switch the CDR refclk Selection Using Embedded Streamer and Reconfiguration Profiles in Arria® 10 Native PHY	Learn how to perform dynamic reconfiguration to switch the clock data recovery (CDR) refclks with embedded streamer and multiple reconfiguration profiles in the Intel® Arria® 10 device.
How to Configure Two FPGAs that is Externally Connected through SMA Cables Using Transceiver Toolkit	Learn how to how to configure two device under test (DUTs), launch transceiver (XCVR) toolkits, perform chip-to-chip interface, and find the right analog settings.
How to Perform Dynamic Reconfiguration to Switch TX PLLs for the Arria® 10 Transceiver Using Embedded Streamer	Learn how to perform dynamic reconfiguration to switch transmitter (TX) PLLs for the Intel® Arria® 10 FPGA transceiver using embedded streamer.

Title	Description
Intel® Arria® 10 Device Configuration of a Simplex Transceiver	Watch this video to learn how to place an Intel® Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.
Dynamic Reconfiguration of an Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel® Arria® 10 devices.
How to Use the Transceiver Toolkit Part 1	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.
How to Use the Transceiver Toolkit Part 2	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 3	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
How to Use the Transceiver Toolkit Part 4	Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel® Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.
Intel® Arria® 10 Transceivers: Pre-Emphasis Basics	Learn the basics of the Intel® Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.
Performing Dynamic Reconfiguration for the Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel® Arria® 10 devices.
Reconfigure Intel® Arria®10 Device Transceivers Using Embedded Streamer	Watch this video to learn how to perform dynamic reconfiguration with the Intel® Arria® 10 device transceiver Standard PCS using the embedded streamer.
Use the IBIS-AMI Model to Estimate Signal Integrity of Intel® Arria® 10 Device Transceiver	Watch this video to learn how to perform a signal integrity simulation with the Intel® Arria® 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.

Title
Is 8b10b encoding supported in the Arria V, Cyclone V or Stratix V transceiver toolkit?
What are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices?
Why can t I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices?
What is the correct XCVR_RX_SD_ENABLE QSF variable setting to turn ON/OFF the signal detect fetaure in Stratix V, Arria V and Cyclone V devices?
What is the reset sequence for high speed GX transceivers in loss of link conditions in Altera GX/GT/GZ device families?
At what stage in the Quartus II compilation process are the MIF files generated for Stratix V, and Arria V devices using transceiver dynamic reconfiguration?
Error (12252): Link_test_sopc_sys.clk.clk_reset/checker_0.csr_clk_reset: Missing connection end (try "Remove Dangling Connections")
What is the latency of the transceiver rx_syncstatus signal de-asserting after the assertion of the rx_enapatternalign signal in Stratix IV GX/T, Arria II GX/Z and Cyclone IV GX devices?
What clock domain are the rx_hi_ber and rx_block_lock signals of the 10GBASE-R PHY IP synchronous to?
Why doesn't the Native PHY compensate for clock frequency differences on Stratix V GX devices using Quartus II software versions 12.1sp1 and earlier?
Why doesn't the Reverse Serial Loopback (RSL) feature work on Arria V GX devices in Quartus II Software versions 12.1sp1 and earlier?
Error (12848): "REF10GCLK" is locked to right side. There is no HSSI strip on right side.
Why does Quartus II assigns incorrect I/O standard for the refclk pin on Arria II GX/GZ and Stratix IV GX/GT devices for ALTGX instances?
How do I map the transceiver toolkit pre-emphasis pre-tap settings to the Quartus II transceiver QSF assignments in Stratix V GX and Arria V GZ devices?
Why do I see bit errors on Rx channel 0 of transceiver block GXBL1 when I de-assert the gxb_powerdown signal of transceiver block GXBL0 when using Cyclone IV GX EP4CGX150 and EP4CGX75 devices?
Error (14024): Parameter "sd_threshold" of instance "gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd" has illegal value "3" assigned to it. Possible parameter values are: "SDLV_15", "SDLV_14", "SDLV_13", "SDLV_12", "SDLV_11", "SDLV_10", "SDLV_9", "SDLV_8", "SDLV_7", "SDLV_6", "SDLV_5", "SDLV_4", "SDLV_3", "SDLV_2", "SDLV_1", "SDLV_0"
Can I safely ignore DIV_CLK critical warnings for the fPLL when used in the 66:40 gearbox ratio on Stratix V GX/GS/GT and Arria V GZ transceivers?
How do I map the transceiver toolkit pre-emphasis 2nd post-tap settings to the Quartus II transceiver QSF assignments in Stratix V GX and Arria V GZ devices?
Why does the Stratix V device Transceiver Toolkit display a "Couldn't grab settings for channel" message when using Quartus II software versions 14.1 and 14.1.1?
Are there any problems with Adaptive Equalization (AEQ) in Stratix IV GX and GT devices?
Error: invalid command name "::alt_xcvr::ip_tcl::ip_module::ip_log_invalid_parameter"
Are the default XAUI PHY IP transceiver PMA settings in Quartus II Software Version 10.1-SP1 and earlier capable of implementing a XAUI compliant link in Stratix IV GX and GT devices?
What is the read latency of an M20K ROM that must be accounted for when performing MIF-based streaming dynamic reconfiguration Stratix V GX devices?
Are Arria II GX/GZ transceivers able to support 1.4V source on VCCH_GXB?
Are there any known problems when trying to simulate the Quartus II software versions 12.1, or 12.1sp1 Altera 10GBASE-KR PHY IP in Cadence ncsim?
Does Altera ALTGX PHY allows lane reversal for a XAUI link (lane 0 to lane 3, lane 1 to lane 2, and so on)?
What are the connection guidelines for the REFCLK pin (GXBR4F) in the Arria 10 10AX115NF40 package?
Why do I get a syntax error related to "Missing or invalid file version" when I try to open Stratix IV GX device Eldo models in Hyperlynx tool?
Why is the input common mode voltage (VICM) of the Arria II GX dedicated transceiver refclk pins lower than the 1.1V device specification?
Why doesn't the generic transceiver Tx and Rx polarity inversion feature work on Stratix V, Arria V, Cyclone V devices with Quartus II Software versions 12.1sp1 and earlier?
How should you connect power, ground (gnd), and input signals on unused High Speed Serial Interface (HSSI) Transceivers (XCVR)s?
What are the PRBS7, PRBS15, PRBS23, and PRBS31 polynomials used in the Altera Transceiver Toolkit?