The Timing Analyzer determines the timing relationships that must be met for the design to correctly function and checks arrival times against required times to verify timing.
Timing analysis involves many foundational concepts: asynchronous v. synchronous arcs, arrival and required times, setup and hold requirements, etc. These are defined in the Timing Analyzer Terminology and Concepts section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer.
The Timing Analyzer applies your timing constraints and determines timing delays from the results of the Fitter's implementation of your design into the target device.
The Timing Analyzer must operate from an accurate description of your timing requirements, expressed as timing constraints. The Constraining Designs section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer describes how timing constraints can be added to .sdc files, for use by both the Fitter and the Timing Analyzer.
Timing closure is an iterative process of refining timing constraints; adjusting parameters for synthesis and the Fitter, and managing fitter seed variations.