Intel® Quartus® Prime Design Software - Support Center

• Pin-Out Files for Intel® FPGA Devices
• Pin Connection Guidelines - per device Family

I/O planning involves many considerations especially when high-speed I/Os or specific protocols are involved. For more information on I/O management and board development support, visit the I/O Management, Board Development Support, and Signal Integrity Analysis Resource Center web page.

Intel offers several HDL training courses, from free online overviews to full day-long instructor-led classes.

HDL coding styles have a significant effect on the quality of results for logic designs. Synthesis tools will optimize the design, but to achieve precise results, you need to code in a style which will be readily recognized by the synthesis tool as specific logic constructs. 

In addition, there are good design practices which should be followed for general digital logic design and for LAB-based devices in particular. Managing logic reset methodologies, pipeline delays, and proper synchronous signal generation are some examples of good digital design practices. Some resources for learning good HDL coding practices are listed below.

Intel® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in Intel® FPGAs. Each IP includes a simulation model for design verification before device implementation. See the following links for more information on available IP cores and the IP ecosystem within the Intel® Quartus® Prime software.

The integration of a HDL simulator into the Intel® Quartus® software tool flow is described in the following section of the Intel® Quartus® software User Guide | Handbook:

• Simulating Intel® FPGA Designs (Pro Edition | Standard Edition)

When using the Platform Designer to configure IP cores and systems, simulation environment setup scripts are generated for supported EDA simulators.

When creating multiple Platform Designer systems, you should run "Generate Simulator Setup Script for IP" to create a combined script for your systems in the Platform Designer. 

• Generating a Combined Simulator Setup Script (Pro Edition | Standard Edition)

You can incorporate generated IP core simulation scripts into a top-level simulation script that controls the simulation of your entire design. After running ip-setup-simulation, use the following information to copy the template sections and modify them for use in a new top-level script file.

• Aldec Active-HDL ( Pro Edition | Standard Edition )
• Aldec Riviera-PRO ( Pro Edition | Standard Edition )
• Cadence Incisive Enterprise ( Pro Edition | Standard Edition )
• Mentor Graphics* ModelSim*-Intel® FPGA Edition (bundled with the Intel® Quartus® Prime software) ( Pro Edition | Standard Edition )
• Mentor Graphics* ModelSim* - PE ( Pro Edition | Standard Edition )
• Mentor Graphics* ModelSim* - SE ( Pro Edition | Standard Edition )
• Mentor Graphics* QuestaSim ( Pro Edition | Standard Edition )
• Synopsys* VCS and VCS MX ( Pro Edition | Standard Edition) 

You can also refer to the following videos for guidance on setting up simulations.

• How to Generate RTL Simulation Scripts for Intel® Quartus® Prime Project 
• ModelSim*-Intel® FPGA Edition Simulation with Intel® Quartus® Prime Pro Edition

In the Intel® Quartus® Prime Standard Edition software, you have the option of using NativeLink. This lets you automatically launch all the steps needed to simulate your design after modifying your source code or IP.

The NativeLink feature integrates your EDA simulator with the Intel® Quartus® Prime Standard Edition software by automating the following:

• Generation of simulator-specific files and simulation scripts.
• Compilation of simulation libraries.
• Automatic launching of your simulator following the Intel® Quartus® Prime software analysis and elaboration, analysis and synthesis, or after a full compilation.

Intel's high-level synthesis (HLS) tool takes in a design description written in C++ and generates RTL code that is optimized for Intel® FPGAs.

For more information on the Intel® HLS Compiler, including documentation, examples, and training courses, view the HLS Support Page.

In the Intel® Quartus® Prime Standard Edition software, you can specify several settings to direct the effort level of the Fitter such as register packing, register duplication and merging, and overall effort level. For a complete listing of Fitter Settings, see Compiler Settings Help Page

For more information on Fitter settings, see discussions under 

• Reducing Compilation Time section in volume 2 of the Intel® Quartus® Prime Standard Edition Handbook
• Timing Closure and Optimization section in volume 2 of the Intel® Quartus® Prime Standard Edition Handbook

The Timing Analyzer in the Intel® Quartus® Prime software is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry standard constraint, analysis, and reporting methodology. The Timing Analyzer can be driven from a graphical user interface or from a command-line interface to constrain, analyze, and report results for all the timing paths in your design.

A full user guide on the Timing Analyzer can be found in the Running the Timing Analyzer section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook.

If you are new to Timing Analysis, see the Recommended Flow for First Time Users section in volume 3 of the Intel® Quartus® Prime Standard Edition Handbook. This describes the full design flow using basic constraints.

If the Timing Analyzer determines that your timing specifications are not met, then the design must be optimized for timing until the discrepancy is closed and your timing specifications are met.

Timing closure involves several possible techniques. The most effective techniques will vary with each design. The Timing Closure and Optimization chapter in the Design Optimization User Guide: Intel Quartus Prime Pro Edition gives a lot of practical advice about the timing closure process.

There are several additional training courses to help you understand how to evaluate your design for the right timing closure techniques.

The Intel® Quartus® Prime software provides tools that present your design in visual ways. These tools let you diagnose any problem areas in your design, in terms of logical or physical inefficiencies.

• You can use the Netlist Viewers to see a schematic representation of your design at several stages in the implementation process: before synthesis, after synthesis, and after place-and-route. This enables you to confirm your design intent at each stage.
• The Design Partition Planner helps you visualize and revine a design's partitioning scheme by showing timing information, relative connectivity densities, and the physical placement of partitions. You can locate partitions in other viewers, or modify or delete partitions.
• With the Chip Planner, you can make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. The Design Partition Planner and the Chip Planner allow you to partition and layout your design at a higher level.
• Design Space Explorer II (DSE) automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.
  

Using these tools can help you optimize the implementation of the device.

Design floorplan analysis helps to close timing and ensure optimal performance in highly complex designs. The  Chip Planner in the Intel® Quartus® Prime software helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock Regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.

You can perform design analysis as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.

Design Space Explorer II (DSE) allows you to explore the many parameters available for design compilation.

You can use the DSE to manage multiple compilations with different parameters to find the best combination of parameters that allow you to achieve timing closure.

• SignalTap II Logic Analyzer State-Based Triggering Flow Design Examples 
• In-System Sources and Probes Example
• Transceiver Toolkit Examples for Stratix® V GX, Arria® V GX/GT, Cyclone® V GX/GT and Stratix® IV GX/GT Devices
• System Console Design Examples (.qar Quartus® software archive format)

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.

You can create multiple personas for a region of your device, and reconfigure that region without impacting operations in areas outside that persona.

For more information on Partial Reconfiguration, see the Partial Reconfiguration page.

The Intel® Quartus® Prime and Quartus® II software includes comprehensive scripting support for command-line and tool command language (Tcl) script design flows. Separate executables for each stage of the software design flow, such as synthesis, fitting, and timing analysis, include options for making common settings and performing common tasks. The Tcl scripting application programming interface (API) includes commands covering basic to advanced functionality. 

Command-Line Scripting

You can use Intel® Quartus® Prime or Quartus® II software command-line executables in batch files, shell scripts, makefiles, and other scripts. For instance, use the following command to compile an existing project:

        $ quartus_sh --flow compile

Tcl Scripting

Use the Tcl API for any of the following tasks:

• Creating and managing projects
• Making assignments
• Compiling designs
• Extracting report data
• Performing timing analysis
  

You can get started with some of the examples in the Quartus® II software Tcl examples web page. Several other resources are listed below.