PCI Express* IP – Support Center

Welcome to the PCI Express* (PCIe*) IP support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.  

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel Stratix® 10, Intel Arria® 10, Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, Knowledge Base.

Refer to Table 1 and Table 2 to understand the PCIe* support for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices. Compare between the three devices to select the right device for your PCIe system implementation.

For earlier device families, please consult the specific FPGA product family pages on the Intel FPGAs Overview page. 

Table 1 - Device Support and Number of Hardened PCIe IP Blocks

Device Family Number of Hardened PCIe IP Blocks PCIe Speed per Lane  

Gen1

(2.5 GTps)

Gen2

(5.0 GTps)

Gen3

(8.0 GTps)

Gen4

(16.0 GTps)

Intel® Stratix® 10 1 to 4 per device
Intel® Arria® 10 1 to 4 per device  
Intel® Cyclone® 10 1 per device    

Table 2. Device Configurations and Features Support

Interface Type Avalon-ST Avalon-MM Avalon-MM with DMA SR-IOV CvP / PRoP
Device/Configuration  
Intel Agilex Endpoint Up to Gen4 x16 Up to Gen4 x16 Up to Gen4 x16 Available Up to Gen4 x16: CvP Init
Root Port Up to Gen4 x16 Up to Gen4 x16 - - -
Intel Stratix 10 Endpoint Up to Gen4 x16 Up to Gen4 x16 Up to Gen4 x16 Available Up to Gen4 x16: CvP Init
Root Port Up to Gen4 x16 Up to Gen4 x16 - - -
Intel Arria 10 Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 Available Up to Gen3 x8: CvP and PRoP
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Intel Cyclone 10 GX Endpoint Up to Gen2 x4 Up to Gen2 x4 Gen2 x4 - Up to Gen2 x4: CvP and PRoP
Rootport Up to Gen2 x4 Up to Gen2 x4 - - -
Stratix V Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
Available Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria V GZ Endpoint Up to Gen3 x8 Up to Gen3 x4 Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8
- Gen1: CvP Init and CvP Update
Gen2: CvP Init and CvP Update
Root Port Up to Gen3 x8 Up to Gen3 x4 - - -
Arria V Endpoint Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

Gen1 x8, Gen2 x4 - Up to Gen1 x8 and Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

- - -
Cyclone V Endpoint Up to Gen2 x4 Up to Gen2 x4 (no x2) Gen2 x4 - Up to Gen2 x4
Gen1: CvP Init and CvP Update
Gen2: CvP Init
Root Port Up to Gen2 x4 Up to Gen2 x4 (no x2) - - -
  • CvP –  Configuration via Protocol
  • PRoP – Partial Reconfiguration over PCI Express
  • SR-IOV – Single Root I/O Virtualization
  • DMA – Direct Memory Access

Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 Device Hardened IP for PCIe*

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack, which includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

 

Intel Stratix 10 Devices User Guides

Intel Arria 10 and Intel Cyclone 10 Devices User Guides

 

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 Devices

Title Description
Intel® Arria® 10 Device Configuration via Protocol (CvP) Learn how to configure your Intel Arria 10 device using the PCIe* protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1) Learn how to set up the PCIe Avalon Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux* and Windows* operating systems from this Part 1 video.
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2) Learn how to set up the PCIe Avalon-MM Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video.

Other Technologies

Intel, Quartus, Stratix, Cyclone and Arria are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

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