PCI Express* IP – Support Center

Welcome to the PCI Express* (PCIe*) IP support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Watch the PCIe* Getting Started Video

Intel® FPGA Device Family

Refer to Table 1 and Table 2 to understand the PCIe* support for Intel® Stratix^®10, Intel Arria® 10, and Intel Cyclone® 10 devices. Compare between the three devices to select the right device for your PCIe system implementation.

For earlier device families, please consult the specific FPGA product family pages on the Intel FPGAs Overview page.

Device Family	Number of Hardened PCIe IP Blocks	PCIe Speed per Lane
Table 1 - Device Support and Number of Hardened PCIe IP Blocks
Device Family	Number of Hardened PCIe IP Blocks	Gen1 (2.5 GTps)	Gen2 (5.0 GTps)	Gen3 (8.0 GTps)
Intel® Stratix® 10	1 to 4 per device	✓	✓	✓
Intel® Arria®10	1 to 4 per device	✓	✓	✓
Intel® Cyclone® 10	1 per device	✓	✓

Interface Type		Avalon® Streaming (Avalon-ST) Interface		Avalon Memory-Mapped (Avalon-MM) Interface		CvP / PRoP
Table 2 - Device Configuration and Feature Support
Device Family	IP Configuration	Avalon-ST	Avalon-ST SR-IOV	Avalon- MM	Avalon-MM DMA
Intel® Stratix® 10	Endpoint	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16 CvP Initialization, Update, and PRoP
Intel® Stratix® 10	Root Port	Up to Gen3x16	NA	Up to Gen3x16	NA	NA
Intel® Arria® 10	Endpoint	Up to Gen3x8	Available	Up to Gen3x4	Gen1x8, Gen2x4, Gen2x8, Gen3x2, Gen3x4, Gen3x8	Up to Gen3x8 CvP Initialization and PRoP only
Intel® Arria® 10	Root Port	Up to Gen3x8	NA	Up to Gen3x4	NA	NA
Intel® Cyclone® 10	Endpoint	Up to Gen2x4	NA	Up to Gen2x4	Up to Gen2x4	Up to Gen2x4 CvP Initialization and PRoP only
Intel® Cyclone® 10	Root Port	Up to Gen2x4	NA	Up to Gen2x4	NA	NA

CvP – Configuration via Protocol
PRoP – Partial Reconfiguration over PCI Express
SR-IOV – Single Root I/O Virtualization
DMA – Direct Memory Access

PCIe Hardened IP User Guides

Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 Device Hardened IP for PCIe*

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack, which includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

Intel Stratix 10 Devices User Guides

Intel Arria 10 and Intel Cyclone 10 Devices User Guides

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

L-Tile/H-Tile Transceiver PHY User Guide

Intel Arria 10 Devices

Transceiver PHY User Guide

Intel Cyclone 10 Devices

GX Transceiver PHY User Guide

Reference Designs

Intel® Stratix® 10 Devices

Intel Arria® 10 Devices

Intel Cyclone® 10 Devices

Gen2x4 DMA Reference Design - Intel Cyclone 10 GX Device (AN 855)

Intel Legacy Devices

Additional Resources

IP Integration

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel® Stratix® 10 Devices

Intel Arria® 10 Devices

How to Implement PCI Express (PIPE) in Arria 10 Transceivers section of the Intel Arria 10 Transceiver PHY User Guide

Intel Cyclone® 10 Devices

How to Implement PCI Express (PIPE) in Intel Cyclone 10 GX Transceivers section of the Intel Cyclone 10 GX Transceiver PHY User Guide

Training Courses

PCIe* Training Courses

Videos

Title	Description
Intel® Arria® 10 Device Configuration via Protocol (CvP)	Learn how to configure your Intel Arria 10 device using the PCIe* protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1)	Learn how to set up the PCIe Avalon Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux* and Windows* operating systems from this Part 1 video.
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2)	Learn how to set up the PCIe Avalon-MM Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video.

Title
Why might my Intel® FPGA PCIe* IP fail to link train in some systems?
What is the maximum payload size I can issue the PCI Express Hard IP on the Avalon-ST TX interface?
Why do the configuration space registers 0x24 to 0x2C in PCIe HIP are not accessible ?
Why does the Hard IP for PCI Express in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?
Why do I receive incorrect data returned from my read TLP requests on my Avalon-Memory Mapped 128 bit Altera Hard IP for PCI Express?
Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?
Why does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?
Why are BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for PCI Express Avalon-MM variant?
Why I can't read PCIe VENDOR_ID register at address offset 0x000?
Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly?
How to access Intel® Stratix® 10 PCI Express* configuration space registers without the Local Management Interface?
Has there been an update to the Arria 10 Soft DFE IP for PCIe Gen3?
Error(175020): The Fitter cannot place logic pin that is part of pcie_example_design pcie_example_design in region (95, 2) to (95, 2), to which it is constrained, because there are no valid locations in the region for logic of this type
Why does my PCIe Stratix 10 L-tile ES2 component display "Please select a valid device to generate the IP" upon generation?
Why does the Intel® Stratix® 10 Hard IP for PCIe* report incorrect link widths?
Why do I see errors, or link training or speed change failures, on my Stratix 10 Hard IP for PCIe?
Why is my Intel® Stratix®10 GX ES device with PCIe* Hard IP unable to transmit TLP packets or show lowered bandwidth?
Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?
How do I assign non 3.0-V I/O standard for nPERST pins of Intel® Stratix10® PCI Express* Hard IP?
Why I cannot access PCIe registers after generating Quartus Prime 16.1 PCIe CvP mode?
Why does time stamp value of Stratix 10 Link Inspector not accurate?
How can I change BAR* Size in the PCI Express Hard IP of Arria® V and Cyclone® V ?
Why do I get sdc warning messages regarding altpcie_ltssm_fifo.sdc and altpcie_link_inspector.sdc, when compiling the design which instantiates the Intel® Stratix® 10 PCIe* IP?
Why isn't Arria 10 Transceiver calibration completed?
Why are timing failures reported from wys~ch3_pcs_chnl_hip_clk_out[0].reg for Intel® Arria® 10 PCIe Gen3 Hard IP?
Why does my OS freeze when using the Stratix 10 PCIe Hard IP core?
Why is app_int_ack status signal not available for PCI Express Hard IP Core of Cyclone V devices
Why do directed speed changes fail when my Intel® Stratix® 10 PCIe* IP requests a speed change from Gen 3?
How do I enable or disable the Advanced Error Detection (AER) for my PCIe* Hard IP core?
Why does my Intel® Stratix® 10 PCIe* IP fail to perform a directed Gen3 or Gen2 speed change or a change to the L1 state?
When should I enable the Soft DFE Controller IP for Arria 10 PCIe HIP?
Why does my Arria 10 PCIe Hard IP link width downtrain?
Why doesn't the Intel® Arria® 10 PCI* Express HIP set pattern lock bit when received modified compliance pattern at LTSSM=Polling Compliance state ?
Why does VCS simulation of Intel® Stratix® 10 PCIe* Hard IP return this RT Warning: More than one conditions match in 'unique case' statement?
Why does Intel® Stratix® 10 PCIe* HIP infers a latch in root port mode?
Why does the Intel® Arria® 10 PCIe* Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register?
Error: add_fileset_file: No such file <Quartus_Installation_Directory>/0002_pcie_s10_hip_ast_0_gen/ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_fpll_s10_htile_181/sim/docs/pcie_example_design_DUT_altera_xcvr_fpll_s10_htile_181_rrbjwya_parameters.csv/pcie_example_design_DUT_altera_xcvr_fpll_s10_htile_181_rrbjwya_parameters.csv
The Intel® Arria® 10 PCIe* Hard IP does not allow a memory write completion TLP to pass a memory read TLP.
Why does the Intel® Arria® 10 PCIe* Hard IP fail to set the pattern lock bit when receiving a modified compliance pattern during the LTSSM=Polling Compliance state?
Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v
How does the tags for non-posted request works in the Intel Arria 10 Avalon-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?
Intel® Arria® 10 Gen3 PCIe* Endpoint is not compatible with PCIe* Gen4 capable system.
Why are the message data allocated vectors (0x05c) in the Intel® Arria® 10 PCIe* MSI capability structure are not writable when multiple message enable is set?
The Intel® Arria® 10 PCIe* Hard IP Avalon®-MM TXS bridge does not support completion without data after sending a memory read request when the RootPort is in any power management D-state.
Why does Retrain Link with Perform Equalization bit set to 1 cause the Intel® Arria® 10 Gen3 PCIe* Root Port to down train to Gen1 speed?
Why does the Arria 10 Hard IP for PCI Express Example Design Generation fail on Windows 7?
What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria 10 ES2, ES3 or production device?
Error (10166): SystemVerilog RTL Coding error at altpcieav_dma_hprxm_rdwr.sv(562): always_comb construct does not infer purely combinational logic.
Is there a VCCA_GXB voltage rail for my Intel® Cyclone® V PCIe* AVMM component, as referenced in the user guide?
Why does Intel Arria 10 or Cyclone 10 GX PCIe* HIP not allow a memory write completion TLP to pass a read memory packet?
How do I enable the RX polarity inversion soft logic of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express?
Why does the Avalon-MM DMA Hard IP for PCIe fail to return data for small DMA transfers?
How do I determine if there is a "RX completion buffer overflow" with the Intel® Arria® 10 or the Intel® Cyclone® 10 PCIe* Avalon®-MM DMA IP core if Platform Designer does not allow the users to enable this option?
Error (suppressible): <your path><your top>.vhd(<your line number>): (vcom-1130) Port "exprom_en_pf" of entity "<...>altera_pcie_a10_hip_170_<random string>" is not in the component being instantiated.
Error(13224): Verilog HDL or VHDL error at altera_pcie_s10_hptxs_tx.sv(<your line number>): index <your index> is out of range [<your range>] for address
Why does the Hard IP for PCI Express keep dl_up asserted, and transmit incorrect TS1 ordered sets when in the Disabled state?
Why does my Cyclone® 10 GX PCIe Hard IP link width downtrain?
Why does the lane_act bus show incorrect link widths for my Stratix 10 H-tile Hard IP for PCI Express?
Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear?
When using the Intel® Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable?
Why does Intel® Stratix® 10 PCIe* Hard IP with SR-IOV drop outstanding completion TLPs of different PFs that use the same tag value?
Hot Reset is not supported in Root Port mode on Intel® Arria® 10 FPGAs.
How can the register values for the Intel® Arria® 10 PCI Express* IP be read or written to?
Why do I see additional BAR’s reported when executing the lscpi command for Intel Arria 10 PCIe Hard IP?
Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_sys.cpp, Line: 3584
Why does the serdes_pll_locked signal of upper PCI Express Hard IP of Intel Cyclone V devices does not lock?
Error (suppressible): (vsim-3584) ./../../altera_pcie_a10_ed_<version>/sim/altpcied_a10_hwtcl.sv(888): Module parameter 'AVALON_ST_256' not found for override.
Why does the 'Number of tags supported' parameter does only show up to 64 tags for non-posted requests in the Intel® Arria® 10 GX Avalon®-ST Interface for PCI Express*?
Why does the 'Size' parameter for the BAR0 to BAR5 is set to 4 by default in the Intel® Arria® 10 GX Avalon®-MM Interface for PCI Express* version 18.0?
Why does Modelsim/Questasim simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM DMA Interface for PCI Express* fail with X propagation problem in the Read Data Mover (altpcieav_dma_rd.sv) module?
Why message data allocated vectors in Arria 10 MSI capability structure are not writeable when multiple message enable is set?
Why does the Intel® Arria® 10 Hard IP for PCI* Express in Root Port mode, LTSSM not stay in the Disabled state when Link Disable bit is set to 1.
Why does Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express IP's dynamic generated example design fail timing on Stratix 10 ES1 and ES2 devices?
No paths exist between clock target "*\|altpcie_a10_hip_pipen1b\|wys\|core_clk_out" of clock "dut\|wys~CORE_CLK_OUT" and its clock source. Assuming zero source clock latency.
Why does my Intel Arria 10 Hard IP for PCI Express fails to send TS1 ordered sets or EIOS and does not indicate link down on entry to disabled state?
Why does synthesis of Intel® Arria® 10 PCIe* IP generated with VHDL return Error(16045) - ""u_global_buffer_coreclkout" instantiates undefined entity "altera_global""?
Why does my Intel® Stratix® 10 PCIe* example design fail to enumerate?
altera_pcie_a10_skp.sdc >> Error: Unable to find the parent of tx_serial_clk in 100 attempts!
Why does Intel® Arria® 10 PCIe* IP Root Port is not updating AER registers when receiving a malformed completion packet?