PCI Express* IP – Support Center

Welcome to the PCI Express* (PCIe*) IP support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, Knowledge Base.

Watch the PCIe* Getting Started Video

Intel® FPGA Device Family

Refer to Table 1 and Table 2 to understand the PCIe* support for Intel® Stratix®10, Intel® Arria® 10, and Intel® Cyclone® 10 devices. Compare between the three devices to select the right device for your PCIe system implementation.

For earlier device families, please consult the specific FPGA product family pages on the Intel FPGAs Overview page.

Table 1 - Device Support and Number of Hardened PCIe IP Blocks

Device Family	Number of Hardened PCIe IP Blocks	PCIe Speed per Lane
Device Family	Number of Hardened PCIe IP Blocks	Gen1 (2.5 GTps)	Gen2 (5.0 GTps)	Gen3 (8.0 GTps)	Gen4 (16.0 GTps)
Intel® Stratix® 10	1 to 4 per device	✓	✓	✓	✓
Intel® Arria®10	1 to 4 per device	✓	✓	✓
Intel® Cyclone® 10	1 per device	✓	✓

Table 2. Device Configurations and Features Support

Interface Type		Avalon®-ST	Avalon-MM	Avalon-MM with DMA	SR-IOV	CvP / PRoP
Device/Configuration
Intel® Agilex™	Endpoint	Up to Gen4 x16	Up to Gen4 x16	Up to Gen4 x16	Available	Up to Gen4 x16: CvP Init
Intel® Agilex™	Root Port	Up to Gen4 x16	Up to Gen4 x16	-	-	-
Intel® Stratix® 10	Endpoint	Up to Gen4 x16	Up to Gen4 x16	Up to Gen4 x16	Available	Up to Gen4 x16: CvP Init
Intel® Stratix® 10	Root Port	Up to Gen4 x16	Up to Gen4 x16	-	-	-
Intel® Arria® 10	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8	Available	Up to Gen3 x8: CvP and PRoP
Intel® Arria® 10	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Intel® Cyclone® 10 GX	Endpoint	Up to Gen2 x4	Up to Gen2 x4	Gen2 x4	-	Up to Gen2 x4: CvP and PRoP
Intel® Cyclone® 10 GX	Rootport	Up to Gen2 x4	Up to Gen2 x4	-	-	-
Stratix® V	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	Available	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Stratix® V	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria® V GZ	Endpoint	Up to Gen3 x8	Up to Gen3 x4	Gen1 x8, Gen2 x4, Gen2 x8 Gen3 x2, Gen3 x4, Gen3 x8	-	Gen1: CvP Init and CvP Update Gen2: CvP Init and CvP Update
Arria® V GZ	Root Port	Up to Gen3 x8	Up to Gen3 x4	-	-	-
Arria® V	Endpoint	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	Gen1 x8, Gen2 x4	-	Up to Gen1 x8 and Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Arria® V	Root Port	Up to Gen1 x8 and Gen2 x4	Up to Gen1 x8 and Gen2 x4 (no x2)	-	-	-
Cyclone® V	Endpoint	Up to Gen2 x4	Up to Gen2 x4 (no x2)	Gen2 x4	-	Up to Gen2 x4 Gen1: CvP Init and CvP Update Gen2: CvP Init
Cyclone® V	Root Port	Up to Gen2 x4	Up to Gen2 x4 (no x2)	-	-	-

CvP – Configuration via Protocol
PRoP – Partial Reconfiguration over PCI Express
SR-IOV – Single Root I/O Virtualization
DMA – Direct Memory Access

User Guides

Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 Device for PCIe*

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack that includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

IP User Guides

Intel® Agilex™ Devices

P-Tile IP User Guides

Intel® Stratix® 10 Devices

P-Tile User Guides

H-Tile/L-Tile User Guides

Intel® Arria® 10 and Intel® Cyclone® 10 Devices User Guides

Design Example User Guides

Intel® Agilex™ Devices

P-Tile Design Example User Guides

Intel® Stratix® 10 Devices

P-Tile Design Example User Guides

L/H-Tile Design Example User Guides

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

IP Release Notes

Intel® Agilex™ Devices

P-Tile IP for PCI Express IP Core Release Notes

Intel® Stratix® 10 Devices

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

Intel Arria 10 and Intel Cyclone 10 Hard IP for PCI Express IP Core Release Notes

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

L-Tile/H-Tile Transceiver PHY User Guide

Intel Arria 10 Devices

Transceiver PHY User Guide

Intel Cyclone 10 Devices

GX Transceiver PHY User Guide

Reference Designs

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

Intel® Cyclone® 10 Devices

Gen2x4 DMA Reference Design - Intel Cyclone 10 GX Device (AN 855)

Intel Legacy Devices

DMA Reference Design for Legacy Devices (AN 456)

Additional Resources

IP Integration

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel® Stratix® 10 Devices

Intel® Arria® 10 Devices

How to Implement PCI Express (PIPE) in Intel Arria 10 FPGA Transceivers section of the Intel Arria 10 FPGA Transceiver PHY User Guide

Intel® Cyclone® 10 Devices

How to Implement PCI Express (PIPE) in Intel Cyclone 10 GX FPGA Transceivers section of the Intel Cyclone 10 GX FPGA Transceiver PHY User Guide

Training Courses

PCIe* Training Courses

Videos

Title	Description
Intel® Arria® 10 Device Configuration via Protocol (CvP)	Learn how to configure your Intel Arria 10 device using the PCIe* protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1)	Learn how to set up the PCIe Avalon Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux* and Windows* operating systems from this Part 1 video.
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2)	Learn how to set up the PCIe Avalon-MM Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video.

Title
Why might my Intel® FPGA PCIe* IP fail to link train in some systems?
Are Jungo WinDriver included in the installation package for Intel® Quartus® Prime software version 19.1?
What is the maximum payload size I can issue the PCI Express Hard IP on the Avalon-ST TX interface?
Why do the configuration space registers 0x24 to 0x2C in PCIe HIP are not accessible ?
Why does the Hard IP for PCI Express in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?
Why do I receive incorrect data returned from my read TLP requests on my Avalon-Memory Mapped 128 bit Altera Hard IP for PCI Express?
Why does the Intel® Hard IP for PCI Express* in Gen3 configurations, periodically transition from the L0 LTSSM state to the Recovery state then back again?
Why does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?
Why are BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for PCI Express Avalon-MM variant?
Why does my Cadence NCSIM Arria V PCIe simulation fail complete getting stuck in L0 and timeout?
How do I simulate the Arria 10, Arria V GZ and Stratix V PCI Express IP cores in Gen3 PIPE Mode?
ERROR: Failed to initialize the S5_CVP library:Failed to initialize the WDC library. Error 0x20000001 - Invalid handle
Why does the Linux re-scan fail when the Class Code of the PCI Express* HIP is configured as all zero ?
Why does the Host system receive corrupted data without LCRC error or Completion Time Out error on a PCIe Gen 3 x16 link that uses the Intel® Stratix® 10 Hard IP for PCI Express* in the Intel® Stratix® 10 L-Tile and H-Tile Devices ?
Why I can't read PCIe VENDOR_ID register at address offset 0x000?
Riviera* Simulation Errors of Intel® Stratix® 10 Avalon®-MM Interface for PCI Express* Solutions
Why does the Intel® L-tile and H-tile Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express* observe correctable errors/link down train when operating in Gen3 Root Port mode?
Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express* and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express* is always 0 regardless of the setting in the IP Catalog ?
Does the Intel® Stratix® 10 L/H-Tile PCI Express* IPs support SRIS?
Why does the Intel® Arria® 10 and Intel Cyclone® 10 PCI* Express Gen1 and Gen2 PIPE PHY fail to link train correctly?
When using the Intel® Arria® 10 PCIe* Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up.
Can the Transceivers Tool Kit be used on transceivers channels instantiated by the Intel® Stratix® 10 Hard IP for PCI Express?
How to access Intel® Stratix® 10 PCI Express* configuration space registers without the Local Management Interface?
Why does the Intel® FPGA P-Tile Debug Toolkit show blank screen when design is loaded?
Why does the BAR offset of the MSI-X Table and PBA for Intel® Stratix® 10 PCI Express* Hard IP fail to take effect?
How do I assign non 3.0-V I/O standard for nPERST pins of Intel® Stratix10® PCI Express* Hard IP?
Why Non-Fatal PCIe* errors are logged in AER with the Intel® FPGA P-Tile/H-Tile , Avalon® Streaming and Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* after boot?
Is the independent PERST# for the Intel® FPGA P-Tile PCI* Express IP ready for user implementation?
Why doesn’t the Upgrade IP Components dialog box in the Intel® Quartus® Prime Pro Edition software version 19.4 require the Intel® FPGA P-Tile IP for PCI Express* version 19.3 to be upgraded?
Error(175020): The Fitter cannot place logic pin that is part of pcie_example_design pcie_example_design in region (95, 2) to (95, 2), to which it is constrained, because there are no valid locations in the region for logic of this type
Has there been an update to the Arria 10 Soft DFE IP for PCIe Gen3?
Why does my PCIe Stratix 10 L-tile ES2 component display "Please select a valid device to generate the IP" upon generation?
Why does the Intel® Stratix® 10 Hard IP for PCIe* report incorrect link widths?
Why do I see errors, or link training or speed change failures, on my Stratix 10 Hard IP for PCIe?
Why is my Intel® Stratix®10 GX ES device with PCIe* Hard IP unable to transmit TLP packets or show lowered bandwidth?
Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?
Why does the reset_status signal toggles after pin_perst signal is released in the Stratix® V Avalon® ST Interface for PCIe* IP?
Why I cannot access PCIe registers after generating Quartus Prime 16.1 PCIe CvP mode?
How do I enable Autonomous Mode in the Intel® Stratix® 10 PCIe* Hard IP?
Does the Intel® Stratix® 10 PCIe* Hard IP support Root Port Mode Configuration Requests?
Why does time stamp value of Stratix 10 Link Inspector not accurate?
How can I change BAR* Size in the PCI Express Hard IP of Arria® V and Cyclone® V ?
Why does the system logs Completion Time out errors on a PCIe link that uses the Intel® Stratix® 10 Hard IP for PCI Express in the Intel Stratix 10 devices?
Why does PCIe* DMA Controller Intel® Stratix® 10 FPGA IP send two continuous MSI interrupt for the DMA operation?
Why does the system console tool in the Intel® Quartus® Prime Pro edition software version 20.2 reports several errors when loading a design that enables PCI Link inspector and includes more than one instance of the Intel® Stratix® 10 Hard IP for PCI Express?
Why do I get sdc warning messages regarding altpcie_ltssm_fifo.sdc and altpcie_link_inspector.sdc, when compiling the design which instantiates the Intel® Stratix® 10 PCIe* IP?
Why does the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer stuck in reset when FLR is initiated?
Is the byte parity in the Intel® Stratix® 10 Avalon® streaming and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express* odd parity ?
Why does the host fail to load the raw binary file(rbf) via Intel® Arria® 10 PCIe* Hard IP for the CvP initialization mode operation?
Why isn't Arria 10 Transceiver calibration completed?
Why are timing failures reported from wys~ch3_pcs_chnl_hip_clk_out[0].reg for Intel® Arria® 10 PCIe Gen3 Hard IP?
Why does my OS freeze when using the Stratix 10 PCIe Hard IP core?
Why is app_int_ack status signal not available for PCI Express Hard IP Core of Cyclone V devices
Why do directed speed changes fail when my Intel® Stratix® 10 PCIe* IP requests a speed change from Gen 3?
How do I enable or disable the Advanced Error Detection (AER) for my PCIe* Hard IP core?
Why does my Intel® Stratix® 10 PCIe* IP fail to perform a directed Gen3 or Gen2 speed change or a change to the L1 state?
Why does the Stratix® 10 DX P-Tile Avalon® Memory Mapped (Avalon-MM) PCIe* IP simulation fail with Quartus® Prime Pro software version 19.4?
When should I enable the Soft DFE Controller IP for Arria 10 PCIe HIP?
Why does my Arria 10 PCIe Hard IP link width downtrain?
Why doesn't the Intel® Arria® 10 PCI* Express HIP set pattern lock bit when received modified compliance pattern at LTSSM=Polling Compliance state ?
Riviera* Simulation Errors of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.
Why doesn t the Soft IP PCIe core send my Avalon-MM memory read request to PCIe bus?
Why does the rx_st_valid signal is not asserted in the Avalon-ST Intel® Stratix® 10 Hard IP for PCI* Express when receive an unsupported request completion?
Why does the Intel® P-Tile Avalon® Memory Mapped Hard IP for PCI Express* Design Example fail to generate When using Windows* software version?
Why does Intel® Stratix® 10 PCIe* HIP infers a latch in root port mode?
Why does VCS simulation of Intel® Stratix® 10 PCIe* Hard IP return this RT Warning: More than one conditions match in 'unique case' statement?
Does the Intel® Stratix® 10 L/H-Tile Hard IP for PCI Express* IP core support lane reversal and polarity inversion.
Why does the Intel® Agilex™ F-Series FPGA Development Kit fail to correctly link train in a Gen3 system?
Why doesn’t the Intel® FPGA IP example design in the Intel® Quartus® Prime Pro Edition software version 19.2 for Windows to be generated?
Why does the Intel® Arria® 10 PCIe* Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register?
Error: add_fileset_file: No such file <Quartus_Installation_Directory>/0002_pcie_s10_hip_ast_0_gen/ip/pcie_example_design/pcie_example_design_DUT/altera_xcvr_fpll_s10_htile_181/sim/docs/pcie_example_design_DUT_altera_xcvr_fpll_s10_htile_181_rrbjwya_parameters.csv/pcie_example_design_DUT_altera_xcvr_fpll_s10_htile_181_rrbjwya_parameters.csv
The Intel® Arria® 10 PCIe* Hard IP does not allow a memory write completion TLP to pass a memory read TLP.
Why does the Intel® Arria® 10 PCIe* Hard IP fail to set the pattern lock bit when receiving a modified compliance pattern during the LTSSM=Polling Compliance state?
Why does the Intel® Arria 10/Cyclone 10 Hard IP for PCI Express with Avalon-MM DMA interface generated example design simulation stopped due to Fatal error?
Why do I see the warning "Associated reset sinks not declared" when using the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express and "Enable dynamic reconfiguration of the PCIe* read-only registers" is enabled?
Why does Intel® Arria® 10 and Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design issue ignored SDC constraint warnings?
Warning (10240): Verilog HDL Always Construct warning at altpciexpav_stif_txresp_cntrl.v
When using Avalon-ST Intel® Stratix® 10 Hard IP for PCI* Express, why does the reset_status signal is not de-asserted when npor is de-asserted?
How does the tags for non-posted request works in the Intel Arria 10 Avalon-ST Interface with SR-IOV PCI Express* core when more than one Physical Function is enabled?
Intel® Arria® 10 Gen3 PCIe* Endpoint is not compatible with PCIe* Gen4 capable system.
Why are the message data allocated vectors (0x05c) in the Intel® Arria® 10 PCIe* MSI capability structure are not writable when multiple message enable is set?
The Intel® Arria® 10 PCIe* Hard IP Avalon®-MM TXS bridge does not support completion without data after sending a memory read request when the RootPort is in any power management D-state.
Why does Retrain Link with Perform Equalization bit set to 1 cause the Intel® Arria® 10 Gen3 PCIe* Root Port to down train to Gen1 speed?
Why does the Intel® L-/H-Tile Avalon® streaming IP for PCI Express* generates a MSI interrupt even when either the 'msi_enable' or the 'Bus Master Enable' bits are not asserted?
When using the Intel® FPGA P-Tile Avalon® streaming IP for PCI* Express, why is an error seen when "Enable Completion Timeout Interface" is selected?
Error: intel_pcie_ptile_ast_0.dummy_user_avmm_rst has an associatedClock of "p1_hip_reconfig_clk" which could not be found
Error: intel_pcie_ptile_ast_0.dummy_user_avmm_rst has an associatedClock of "p0_hip_reconfig_clk" which could not be found
Why does the Lane Equalization Control Register of Intel® Arria® 10 PCIe* Hard IP store the incorrect initial preset value at Endpoint Gen3 mode ?
When using the Intel® FPGA P-Tile Avalon streaming IP for PCI* Express with a 125MHz application clock frequency does the timing analyser report 250MHz being used?
Why doesn't the Intel Stratix 10 Avalon-MM Interface PCIe HIP reflect MSI-X parameters in the IP Catalog ?
Error (10166): SystemVerilog RTL Coding error at altpcieav_dma_hprxm_rdwr.sv(562): always_comb construct does not infer purely combinational logic.
Why does the Arria 10 Hard IP for PCI Express Example Design Generation fail on Windows 7?
What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Arria 10 ES2, ES3 or production device?
ERROR : Expected ARI Control = 0x00000000 -- Actual = 0x00000100
Why does my Intel® FPGA P-Tile Avalon® Streaming (Avalon-ST) IP for PCI Express* Avalon-ST RX interface behave differently depending of the reset condition?
Error intel_pcie_ptile_ast_0(of type intel_pcie_ptile_ask 2.0.0)must be upgraded for use in ACDS20.2
Why does the Bursting Avalon -MM Master (BAM) interface of the Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI* Express and the Intel P-Tile Avalon® -MM IP for PCI* Express have incorrect address ?
Why does the Data transfer test is hang when running Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCIe in Intel® Quartus® Prime Pro Edition software version 19.4?
Why Intel® Arria® 10 Avalon® -ST Interface for PCI Express* Transaction Layer Configuration Space access is not stable?
Why does my Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* End Point show lower read performance with Intel® Quartus® Prime Pro version 19.3?
Are there Linux-based device driver and user application software that can be used for Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCI Express* dynamically generated example designs?
Is there a VCCA_GXB voltage rail for my Intel® Cyclone® V PCIe* AVMM component, as referenced in the user guide?
Why does Intel Arria 10 or Cyclone 10 GX PCIe* HIP not allow a memory write completion TLP to pass a read memory packet?
How do I enable the RX polarity inversion soft logic of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI* Express?
Why does not the Intel® FPGA P-Tile Avalon® Memory mapped IP for PCI Express* support 500MHz PLD Clock Frequency in the Intel® Quartus® Prime Pro Edition software 20.4 ?
Why do I get error "Unknown uid = xhip_block_1_1" when executing the a10_disableiei.tcl script to disable electrical idle inference for Intel® Arria® 10 and Intel® Cyclone® 10 GX PCI-SIG Compliance Base Board (CBB) design?
Warning (332174): Ignored filter at altera_pci_express.sdc(275): <pcie_instance_hierarchy>\|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b\|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy\|fpll_g1g2x1:g_pll.g_pll_g1g2x1.fpll_g1g2x1\|altera_xcvr_fpll_a10:fpll_g1g2x1\|tx_bonding_clocks[0] could not be matched with a clock File: <pcie_instance_ip_directory_path>altera_pcie_a10_hip_181/synth/altera_pci_express.sdc Line: 275
Error: Failed to generate example design example_design to: /current_directory/intel_pcie_ptile_avmm_0_example_design
Why does the Avalon-MM DMA Hard IP for PCIe fail to return data for small DMA transfers?
How do I determine if there is a "RX completion buffer overflow" with the Intel® Arria® 10 or the Intel® Cyclone® 10 PCIe* Avalon®-MM DMA IP core if Platform Designer does not allow the users to enable this option?
Why does the port "sta_hd_altpe3_hip_core_top_hd_altpe3_hip_core_u_clkmux_core_clk_cnt_reg_0_0_q" generated in the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* Verilog file is different from the port name in the EDA netlist?
Why there is an error when compile the Intel® P-Tile Avalon® Memory Mapped Hard IP for PCI Express* Design Example in Gen4x4 Root Port mode?
Why is the Intel® FPGA P-Tile Avalon® memory mapped IP for PCI Express* GUI showing incorrect data bus width and clock frequency?
Why does the Intel® Arria® 10 PCIe* Avalon®-MM with DMA example design hang the Linuix sometimes?
What is the correct clock to use for the application clock domain when using the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*?
What is the bit description of the power management signal of Intel® FPGA P-Tile Avalon® Streaming IP for PCIe Express*?
Error (suppressible): <your path><your top>.vhd(<your line number>): (vcom-1130) Port "exprom_en_pf" of entity "<...>altera_pcie_a10_hip_170_<random string>" is not in the component being instantiated.
Error(13224): Verilog HDL or VHDL error at altera_pcie_s10_hptxs_tx.sv(<your line number>): index <your index> is out of range [<your range>] for address
Why does the Hard IP for PCI Express keep dl_up asserted, and transmit incorrect TS1 ordered sets when in the Disabled state?
Why does my Cyclone® 10 GX PCIe Hard IP link width downtrain?
Why does the lane_act bus show incorrect link widths for my Stratix 10 H-tile Hard IP for PCI Express?
Why does the Intel® Arria 10® PCI Express* Hard IP lane error status register fail to clear?
How can the register values for the Intel® Arria® 10 PCI Express* IP be read or written to?
Why does Intel® Stratix® 10 PCIe* Hard IP with SR-IOV drop outstanding completion TLPs of different PFs that use the same tag value?
Hot Reset is not supported in Root Port mode on Intel® Arria® 10 FPGAs.
When using the Intel® Arria® 10 PCIE* IP core, does assertion of a correctable error during speed change from Gen3 x1/x2 to Gen1 or Gen2 mean the link is unreliable?
Why does Intel® Arria® 10 Hard IP for PCI* Express signal tx_out periodically transition to high impedance in simulation at LTSSM = Recovery Speed state?
Why do I see additional BAR’s reported when executing the lscpi command for Intel Arria 10 PCIe Hard IP?
Why does Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express IP's dynamic generated example design fail timing on Stratix 10 ES1 and ES2 devices?
Error(16186): Can't elaborate top-level user hierarchy
Does the Intel® Stratix® 10 Avalon®-ST Hard IP for PCI Express* IP support 3 physical functions (PFs) in the Intel Quartus® Prime Pro Edition software version 18.0?
Why does the serdes_pll_locked signal of upper PCI Express Hard IP of Intel Cyclone V devices does not lock?
Error (suppressible): (vsim-3584) ./../../altera_pcie_a10_ed_<version>/sim/altpcied_a10_hwtcl.sv(888): Module parameter 'AVALON_ST_256' not found for override.
Why does the 'Number of tags supported' parameter does only show up to 64 tags for non-posted requests in the Intel® Arria® 10 GX Avalon®-ST Interface for PCI Express*?
Why does Modelsim/Questasim simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM DMA Interface for PCI Express* fail with X propagation problem in the Read Data Mover (altpcieav_dma_rd.sv) module?
Why message data allocated vectors in Arria 10 MSI capability structure are not writeable when multiple message enable is set?
Why does the Intel® Arria® 10 Hard IP for PCI* Express in Root Port mode, LTSSM not stay in the Disabled state when Link Disable bit is set to 1.
Why does the Intel® Stratix® 10 PCIe* Avalon®-MM with DMA example design hang the Linux sometimes?
Why does the 'Size' parameter for the BAR0 to BAR5 is set to 4 by default in the Intel® Arria® 10 GX Avalon®-MM Interface for PCI Express* version 18.0?
Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_sys.cpp, Line: 3584
Does the Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP support changing the BAR size at run-time before enumeration?
Why does the Intel® Stratix® 10 Avalon®-MM Interface for PCIe* IP with internal DMA send out the read mover "Done" status before it completes the data transfer?
Are there any issues when host CPU triggers configuration via PCIe for Intel® Stratix® 10 devices in Intel® Quartus® Prime Pro Edition software version 20.3?
Why can't the Link Equalization Request bit be cleared by software when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCIe* IP operating in Root Port mode?
Why does the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP with External descriptor controller example design hang when more than 8 descriptors is programmed?
Why does the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP fail to respond the inbound memory read TLP with Relaxed Ordering bit set ?
Why there is an error when simulate Intel® P-Tile Avalon® Memory Mapped Hard IP for PCI Express* Design Example with debug toolkit feature enabled?
Error(11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.stfabric.demux: "Number of Output Ports" (numOutputInterfaces) 22 is out of range: 1-16
Why does the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP fail to respond the inbound memory read TLP with No Snoop bit set ?
Error (16045): Instance "pcie1\|pcie_a10_hip_0\|altpcie_a10_hip_pipen1b\|g_xcvr.altpcie_a10_hip_pllnphy\|g_xcvr.g_phy_g3x8.phy_g3x8" instantiates undefined entity "phy_g3x8"…
Why does the Intel® Stratix® 10 Avalon®-MM Interface for PCIe* with DMA example design fail the link test and the DMA test when using the default selected BAR0?
When using the Intel® FPGA P-Tile Avalon® memory-mapped IP for PCI* Express, why the "PCIe0 Link" tab in the IP GUI is missing?
Bash: ./altera_cvp_load: /bin/sh^M: bad interpreter: No such file or directory
No paths exist between clock target "*\|altpcie_a10_hip_pipen1b\|wys\|core_clk_out" of clock "dut\|wys~CORE_CLK_OUT" and its clock source. Assuming zero source clock latency.
Why does my Intel Arria 10 Hard IP for PCI Express fails to send TS1 ordered sets or EIOS and does not indicate link down on entry to disabled state?
Why does synthesis of Intel® Arria® 10 PCIe* IP generated with VHDL return Error(16045) - ""u_global_buffer_coreclkout" instantiates undefined entity "altera_global""?
altera_pcie_a10_skp.sdc >> Error: Unable to find the parent of tx_serial_clk in 100 attempts!
Why does my Intel® Stratix® 10 PCIe* example design fail to enumerate?
What should I do with the skp_os output on the PCIe Hard IP in Quartus 16.0?
How do I enable SKP Ordered Set Detection logic in the Arria 10 Hard IP core for PCI Express?
Why is the class code readout of the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCIe* IP different from the class code value set in the IP GUI?
Why does Intel® Stratix ® 10 Avalon®-ST and SR-IOV Interface for PCI Express* IP show BAR size of 7 bits is supported?
Why does Intel® Arria® 10 PCIe* IP Root Port is not updating AER registers when receiving a malformed completion packet?
Why does the Intel Arria 10 PCIe IP Core report unconstrainted clocks?