Refer to Table 1 and Table 2 to understand the PCIe support for Intel® FPGAs. Compare between the devices to select the right device for your PCIe system implementation.

Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 Device for PCIe

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack that includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

IP User Guides

Intel® Agilex™ Devices

    R-Tile IP User Guides

• Intel® FPGA R-Tile Avalon® Streaming IP for PCI Express User Guide

    P-Tile IP User Guides

• Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express User Guide
• Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express User Guide
• Multi Channel DMA for PCI Express IP User Guide

Intel® Stratix® 10 Devices

    P-Tile User Guides

• Intel® FPGA P-Tile Avalon®-ST Hard IP for PCI Express User Guide
• Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express User Guide
• Multi Channel DMA for PCI Express IP User Guide

    H-Tile/L-Tile User Guides

• Multi Channel DMA for PCI Express IP User Guide
• Avalon® Memory Mapped (Avalon-MM) Intel® Stratix® 10 Hard IP+ for PCI Express Solutions User Guide
• Intel® Stratix® 10 H-Tile/L-Tile Avalon Memory Mapped (AvalonMM) Hard IP for PCI Express User Guide
• Intel® Stratix® 10 Avalon Streaming (Avalon-ST) and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User Guide
• Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Intel® Arria® 10 and Intel® Cyclone® 10 Devices User Guides

• Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon Memory Mapped (Avalon-MM) Interface for PCI Express User Guide
• Intel® Arria® 10 or Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) DMA Interface for PCI Express Solutions User Guide
• Intel® Arria® 10 and Intel Cyclone 10 GX Avalon®-ST Interface for PCI Express User Guide
• Intel® Arria® 10 Avalon Streaming (Avalon-ST) Interface with SR-IOV PCIe Solutions User Guide
• Intel® Quartus® Prime Pro Edition User Guide Partial Reconfiguration
• Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

Design Example User Guides

Intel® Agilex™ Devices

    R-Tile Design Example User Guides

• Intel® FPGA R-Tile Avalon® Streaming (Avalon-ST) IP for PCI Express Design Example User Guide

    P-Tile Design Example User Guides

• Intel® FPGA P-Tile Avalon® Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
• Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express Design Example
• Multi Channel DMA for PCI Express IP Design Example User Guide

Intel® Stratix® 10 Devices

    P-Tile Design Example User Guides

• Intel® FPGA P-Tile Avalon® Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
• Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express Design Example
• Multi Channel DMA for PCI Express IP Design Example User Guide
  

    L/H-Tile Design Example User Guides

• Multi Channel DMA for PCI Express IP Design Example User Guide
• Intel® Stratix® 10 Avalon Streaming (Avalon-ST) IP for PCIe Design Example User Guide
• Intel® Stratix® 10 Avalon -MM Hard IP for PCIe Design Example User Guide

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

• Intel® Arria® 10 and Intel® Cyclone® 10 Avalon-ST Hard IP for PCIe Design Example User Guide
• Intel® Arria® 10 and Intel® Cyclone® 10 Avalon-MM Interface for PCIe Design Example User Guide

IP Release Notes

Intel® Agilex™ Devices

• P-Tile IP for PCI Express IP Core Release Notes
• Multi Channel DMA for PCI Express IP Release Notes
  

Intel® Stratix® 10 Devices

• L/H-Tile Hard IP for PCI Express IP Core Release Notes
• P-Tile IP for PCI Express IP Core Release Notes
• Multi Channel DMA for PCI Express IP Release Notes
  

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

• Intel® Arria® 10 and Intel® Cyclone® 10 Hard IP for PCI Express IP Core Release Notes

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

• L-Tile/H-Tile Transceiver PHY User Guide

Intel Arria 10 Devices

• Transceiver PHY User Guide

Intel Cyclone 10 Devices

• GX Transceiver PHY User Guide

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel® Stratix® 10 Devices

• How to Implement PCI Express (PIPE) in Intel® Stratix® 10 FPGA Transceivers section of the Intel Stratix L- and H-Tile Transceiver PHY User Guide
• AN 778: Intel® Stratix® 10 Transceiver Usage Application Note

Intel® Arria® 10 Devices

• How to Implement PCI Express (PIPE) in Intel® Arria® 10 FPGA Transceivers section of the Intel Arria 10 FPGA Transceiver PHY User Guide

Intel® Cyclone® 10 Devices

• How to Implement PCI Express (PIPE) in Intel® Cyclone® 10 GX FPGA Transceivers section of the Intel Cyclone 10 GX FPGA Transceiver PHY User Guide

• PCIe Training Courses

Intel® Agilex™ Devices

• P-Tile IP for PCI Express IP Core Release Notes
• Multi Channel DMA for PCI Express IP Release Notes

Intel® Stratix® 10 Devices

• Intel® Stratix® 10 Multi Channel DMA for PCI Express IP Release Notes
• L/H-Tile Hard IP for PCI Express IP Core Release Notes
• P-Tile IP for PCI Express IP Core Release Notes
  

Intel® Arria® 10 and Intel® Cyclone® 10 Devices

• Intel® Arria® 10 and Intel® Cyclone® 10 Hard IP for PCI Express IP Core Release Notes

• Migrating to Intel® Stratix® 10 Devices from Intel® Arria® 10 Devices for the Avalon®-MM and Avalon-MM DMA Interfaces AN 790
• Migrating to Intel® Stratix® 10 Devices for the Avalon Streaming Interface AN 791