PCI Express* IP – Support Center

Welcome to the PCI Express* (PCIe*) IP support center!

Here you will find information on how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Watch the PCIe* Getting Started Video

Which Intel FPGA Device Family Should I Use?

Refer to Table 1 and Table 2 to understand the PCIe* support for Intel® Stratix^®10, Intel Arria® 10, and Intel Cyclone® 10 devices. Compare between the three devices to select the right device for your PCIe system implementation.

For earlier device families, please consult the specific FPGA product family pages on the Intel FPGAs Overview page.

Device Family	Number of Hardened PCIe IP Blocks	PCIe Speed per Lane
Table 1 - Device Support and Number of Hardened PCIe IP Blocks
Device Family	Number of Hardened PCIe IP Blocks	Gen1 (2.5 GTps)	Gen2 (5.0 GTps)	Gen3 (8.0 GTps)
Intel® Stratix® 10	1 to 4 per device
Intel® Arria®10	1 to 4 per device
Intel® Cyclone® 10	1 per device

Interface Type		Avalon® Streaming (Avalon-ST) Interface		Avalon Memory-Mapped (Avalon-MM) Interface		CvP / PRoP
Table 2 - Device Configuration and Feature Support
Device Family	IP Configuration	Avalon-ST	Avalon-ST SR-IOV	Avalon- MM	Avalon-MM DMA
Intel® Stratix® 10	Endpoint	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16	Up to Gen3x16 CvP Initialization, Update, and PRoP
Intel® Stratix® 10	Root Port	Up to Gen3x16	NA	Up to Gen3x16	NA	NA
Intel® Arria® 10	Endpoint	Up to Gen3x8	Available	Up to Gen3x4	Gen1x8, Gen2x4, Gen2x8, Gen3x2, Gen3x4, Gen3x8	Up to Gen3x8 CvP Initialization and PRoP only
Intel® Arria® 10	Root Port	Up to Gen3x8	NA	Up to Gen3x4	NA	NA
Intel® Cyclone® 10	Endpoint	Up to Gen2x4	NA	Up to Gen2x4	Up to Gen2x4	Up to Gen2x4 CvP Initialization and PRoP only
Intel® Cyclone® 10	Root Port	Up to Gen2x4	NA	Up to Gen2x4	NA	NA

CvP – Configuration via Protocol
PRoP – Partial Reconfiguration over PCI Express
SR-IOV – Single Root I/O Virtualization
DMA – Direct Memory Access

Which PCIe IP Core Should I Use?

Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 Device Hardened IP for PCIe*

The PCIe* IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack, which includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft logic blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

Intel® Stratix® 10 Devices

Intel Arria® 10 and Intel Cyclone® 10 Devices

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

Intel Stratix 10 L-Tile/H-Tile Transceiver PHY User Guide

Intel Arria 10 Devices

Intel Arria 10 Transceiver PHY User Guide

Intel Cyclone 10 Devices

Intel Cyclone 10 GX Transceiver PHY User Guide

Additional Resources

Where Can I Find Information on IP Integration?

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel® Stratix® 10 Devices

Intel Arria® 10 Devices

How to Implement PCI Express (PIPE) in Arria 10 Transceivers section of the Intel Arria 10 Transceiver PHY User Guide

Intel Cyclone® 10 Devices

How to Implement PCI Express (PIPE) in Intel Cyclone 10 GX Transceivers section of the Intel Cyclone 10 GX Transceiver PHY User Guide

Pin Connection Guidelines

Intel® Stratix® 10 Devices

Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Intel Arria® 10 Devices

Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel Cyclone® 10 Devices

Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Schematic Review

Intel® Stratix® 10 Devices

Intel Stratix 10 GX, MX, and SX Schematic Review Worksheet

Intel Arria® 10 Devices

Intel Arria 10 GX, GT, and SX Schematic Review Worksheet

Intel Cyclone® 10 Devices

Intel Cyclone 10 GX Schematic Review Worksheet

Board Layout Guidelines

Board Layout Test

Early Power Estimator

Early Power Estimator (EPE) and Power Analyzer

Thermal Power Guidelines

Intel® Stratix® 10 Device Thermal Power Guidelines - coming soon

Power Sequencing Guidelines

AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel Arria® 10, and Intel Stratix® 10 Devices

PCI-SIG* Integrators Lists

Design Examples and Reference Designs

Intel Stratix® 10 Devices

Intel® Arria® 10 Devices and Intel® Cyclone® 10 Devices

Additional Resources

Training Courses

PCIe* Training Courses

Videos

Title	Description
Intel® Arria® 10 Device Configuration via Protocol (CvP)	Learn how to configure your Intel Arria 10 device using the PCIe* protocol.
PCIe Avalon®-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1)	Learn how to set up the PCIe Avalon Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux* and Windows* operating systems from this Part 1 video.
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2)	Learn how to set up the PCIe Avalon-MM Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video.