DisplayPort IP – Support Center

Welcome to the DisplayPort intellectual property (IP) core support center!

Here you will find information on how to plan, select, design, implement, and verify your DisplayPort IP cores. There are also guidelines on how to bring up your system and debug the DisplayPort links. This page is organized into categories that align with a DisplayPort system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

Which Intel® FPGA Device Family Should I Use?

Link Rate Supported by Device Family

Device Family	Dual Symbol (20 Bit Mode)	Quad Symbol (40 Bit Mode)	FPGA Fabric Speed Grade
Intel® Stratix® 10 (H-tile and L-tile)	RBR, HBR, HBR2	RBR, HBR, HBR2, HBR3	Note: HBR3 support 1, 2 is preliminary
Intel Arria® 10	RBR, HBR, HBR2	RBR, HBR, HBR2, HBR3	1, 2
Intel Cyclone® 10 GX	RBR, HBR, HBR2	RBR, HBR, HBR2, HBR3	5, 6
Stratix V	RBR, HBR, HBR2	RBR, HBR, HBR2	1, 2, 3
Arria V GX/GT/GS	RBR, HBR	RBR, HBR, HBR2	3, 4, 5
Arria V GZ	RBR, HBR, HBR2	RBR, HBR, HBR2	Any supported speed grade
Cyclone V	RBR, HBR	RBR, HBR	Any supported speed grade

What is the DisplayPort Intel FPGA IP Core FPGA Resource Utilization?

The table below shows the resource information for Arria® V and Cyclone® V devices using M10K;

Intel® Arria 10, Intel Stratix® 10, and Stratix V devices using M20K.

The resources were obtained using the following parameter settings:

Mode = simplex
Maximum lane count = 4 lanes
Maximum video input color depth = 8 bits per color (bpc)
Pixel input mode = 1 pixel per clock

Device	Streams	Directions	Symbol per Clock	ALMs	Logic Registers		Memory
Device	Streams	Directions	Symbol per Clock	ALMs	Primary	Secondary	Bits	M10K or M20K
Intel Stratix 10	SST (Single Stream)	RX	Dual	4,967	6,748	884	16,256	11
Intel Stratix 10	SST (Single Stream)	RX	Quad	6,976	8,344	1,112	18,816	14
		TX	Dual	4,800	6,353	533	12,176	15
		TX	Quad	7,716	8,853	641	22,688	29
Intel Arria 10	SST (Single Stream)	RX	Dual	4,322	6,851	1,283	28,288	13
		RX	Quad	9,297	10,955	1,319	34,496	36
		TX	Dual	4,978	6,330	955	12,664	15
		TX	Quad	8,264	8,545	1,156	17,096	13
	MST (4 Streams)	RX	Quad	36,403	38,337	2,700	105,728	88
	MST (4 Streams)	TX	Quad	41,999	55,483	6,000	99,808	86
Intel Cyclone 10 GX	SST (Single Stream)	RX	Dual	4,322	6,851	1,283	28,288	13
		RX	Quad	9,297	10,955	1,319	34,496	36
		TX	Dual	4,978	6,330	955	12,664	15
		TX	Quad	8,264	8,545	1,156	17,096	13
Arria V GX	SST	RX	Dual	7,677	9,786	661	19,648	36
		RX	Quad	9,247	11,114	900	34,496	36
		TX	Dual	8,263	10,304	320	22,816	20
		TX	Quad	12,660	13,040	1,243	33,632	31
	MST (2 Streams)	RX	Quad	17,996	19,619	1,884	51,328	54
	MST (2 Streams)	TX	Quad	22,601	26,302	2,488	57,792	62
Cyclone V GX	SST	RX	Dual	6,236	7,619	2,864	19,648	36
		RX	Quad	7,769	8,925	3,190	34,496	36
		TX	Dual	8,222	10,267	494	22,816	20
		TX	Quad	12,628	13,003	1,359	33,632	31
Stratix V GX/Arria V GZ	SST	RX	Dual	7,743	9,972	563	19,648	36
		RX	Quad	9,344	11,420	732	34,496	36
		TX	Dual	6,725	10,067	645	22,816	20
		TX	Quad	12,168	13,060	1,223	33,632	31
	MST (4 Streams)	RX	Quad	31,079	27,789	3,108	56,320	48
	MST (4 Streams)	TX	Quad	33,218	30,363	2,613	45,696	68

This section contains tables showing IP core variation size and performance examples.

The above table lists the resources and expected performance for selected variations.

The results were obtained using the Intel Quartus^® Prime Software v19.1 for the following devices:

Intel Arria 10 (10AX115S2F45I1SG)
Intel Cyclone 10 GX (10CX220YF780E5G)
Intel Stratix 10 (1SG280HU1F50E2VGS1)
Arria V (5AGXFB3H4F40C5)
Cyclone V (5CGTFD9E5F35C7)
Stratix V (5SGXEA7K2F40C2)

What is the DisplayPort-related information/documentation available?

How do I generate the DisplayPort IP core?

To generate the DisplayPort IP core, follow these steps:

Create an Intel® Quartus® Prime software project using the New Project Wizard available from the File menu.
On the Tools menu, click IP Catalog.
Under Installed IP, double-click Library > Interface Protocols > Audio &Video > DisplayPort Intel FPGA IP. The parameter editor appears.
In the parameter editor, specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the targeted Intel FPGA family and output file HDL preference. Click OK.
Specify parameters and options in the DisplayPort parameter editor: Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided). Specify parameters defining the IP core functionality, port configurations, and device-specific features. Specify options for processing the IP core files in other EDA tools.
Click Generate to generate the IP core and supporting files, including simulation models.
Click Close when file generation completes.
Click Finish.
If you generate the DisplayPort Intel FPGA IP core instance in an Intel Quartus Prime software project, you are prompted to add Intel Quartus Prime software IP File (.qip) and Intel Quartus Prime software Simulation IP File (.sip) to the current Intel Quartus Prime software project.

Similarly, the above steps can be found in the DisplayPort IP Core User Guide:

Steps to generate DisplayPort IP Core in the Intel Quartus Prime software

What is supported in the Quartus generated DisplayPort design example?

The DisplayPort Intel FPGA IP core design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module. Below table represent design example options available for 10-series device.

Design Example	Designation	Data Rate	Channel Mode	Loopback Type
DisplayPort SST parallel loopback with PCR	DisplayPort SST	HBR3, HBR2, HBR, and RBR	Simplex	Parallel with PCR
DisplayPort SST parallel loopback without PCR	DisplayPort SST	HBR3, HBR2, HBR, and RBR	Simplex	Parallel without PCR

Note: For Intel^® Stratix^® 10 Devices, HBR3 support is preliminary.

How do I generate the Quartus DisplayPort design example?

For 10-series device, use the DisplayPort Intel® FPGA parameter editor in the Intel Quartus® Prime Pro Edition software to generate the design example.

Click Tools > IP Catalog, and select target device family.
In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named .ip.
You may select a specific FPGA device in the Device field, or keep the default Intel Quartus Prime software device selection.
Click OK. The parameter editor appears.
Configure the desired parameters for both TX and RX. Note: The DisplayPort design example generation flow supports only SST. Selecting the Support MST parameter prevents you from generating the example design.
On the Design Example tab, select DisplayPort SST Parallel Loopback With PCR or DisplayPort SST Parallel Loopback Without PCR .
Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
For Target Development Kit, select the available Intel FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit.
Click Generate Example Design.

Similarly, the links below provides step-by-step instruction to generate DisplayPort design example from the Intel Quartus Prime software:

How do I compile and test my design?

For 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design Example User Guides, under section "Compiling and Testing the Design":

How can I perform DisplayPort functional simulation?

For 10-series device, below are the steps to generate DisplayPort functional simulation:

Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example.
Perform the simulation
Understanding the testbench

Where do I find information on the Clock Recovery Core?

The 10-series DisplayPort design example uses Pixel Clock Recovery IP. The Clock Recovery Core information can be found in the link below:

Intel® DisplayPort IP Core User Guide

Where do I find information on the DisplayPort Link Training flow?

Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink. The information about the Link Training process can be found at the following link:

Intel® DisplayPort IP Core User Guide

Where do I find information on the DisplayPort API reference and DPCD information?

The following links will direct you to the DisplayPort application programming interface (API) reference and DPCD information:

Pin Connection Guidelines

Intel® Stratix® 10 Devices

Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Intel Arria® 10 Devices

Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel Cyclone® 10 Devices

Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Schematic Review

Intel® Stratix® 10 Devices

Intel Arria® 10 Devices

Intel Cyclone® 10 Devices

Board Design Guidelines

Board Design Guidelines Solutions
Board Layout Test
AN 114: Board Design Guidelines for Intel® Programmable Device Packages
AN 766: Intel Stratix® 10 Devices, High-Speed Signal Interface Layout Design Guideline
AN 613: PCB Stackup Design Considerations for Intel FPGAs
AN745: Design Guideline for Intel FPGA DisplayPort Interface (HTML | PDF)
FMC DisplayPort Daughter Card Revision 8 Schematics
FMC DisplayPort Daughter Card Revision 11 Schematics
HSMC DisplayPort 1.2 Daughter Card Schematics

Disclaimer: The Intel Arria® 10 and Intel Stratix 10 Development Kit on-board DisplayPort TX board design implementation is NOT recommended as it does not allow PMA + PCS bonding. Users are advised to refer tp the Bitec design implementation.

Power Management

Thermal Power Management

Intel® Stratix® 10 Devices

AN 787: Intel Stratix 10 Thermal Modeling and Management (HTML | PDF)

Power Sequencing

Intel® Stratix® 10, Intel Cyclone® 10, and Intel Arria® 10 Devices

AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices (HTML | PDF)

My design require Bitec FMC daughter card. How do I select them?

The following table provides a quick guideline in selecting Bitec FMC daughtercard revision

Bitec FMC Daughtercard Revision	Supported Data Rate
Revision 8 and older revision	RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(5.4 Gbps)
Revision 10 and beyond	RBR(1.62 Gbps), HBR(2.7 Gbps), HBR2(2.7 Gbps), HBR3(8.1 Gbps)

Any requirement to use single or dual lanes transceiver channel with Bitec FMC daughter card for 10-series devices?

Yes. For DisplayPort design that uses/referred to in an early version of Bitec FMC daughtercard (revision 9 and earlier), the pin assignment in the following link has to be followed at TX and RX due to the lane reversal and polarity inversion at the channel.

Device	Device Part Number	Link to Pin Assignment Guide
Intel® Stratix® 10 Device	1SG280HU1F 50E2VGS1	Intel Stratix 10 FPGA Design Example User Guide
Intel Arria® 10 Device	10AX115S2F 45I1SG	Intel Arria 10 FPGA Design Example User Guide
Intel Cyclone® 10 Device	10CX220YF7 80E5G	Intel Cyclone 10 FPGA Design Example User Guide

How do I create a DisplayPort TX-only or RX-only design?

A general guideline to create a DisplayPort TX-only or RX-only design can be found in the Intel® DisplayPort Design Example User Guide. Alternatively, a more detailed explanation specific to the DisplayPort TX-only design can be referred to in the AN 883: Intel Arria® 10 DisplayPort TX-only Design User Guide.

Design Examples and Reference Designs

Intel® Arria® 10 Devices