Boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. This BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. Boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results. Figure 1 illustrates the concept of boundary-scan testing.
Figure 1. IEEE Std. 1149.1 Boundary-Scan Testing
Boundary-scan tools feature an in-system programmability (ISP) capability which utilizes the IEEE Standard 1149.1 controller for Altera® devices including MAX® II, MAX 3000A, MAX 7000AE and MAX 7000B devices. These devices also support IEEE 1532 programming which utilizes the IEEE Standard 1149.1 Test Access Port (TAP) interface.
- AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices (PDF)
- IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices (PDF) chapter of the MAX II Handbook.
Frequently Asked Questions
- Is the Bus-Hold feature in MAX 7000B devices active during JTAG BST and ISP?
- What is the state of I/O pins after EXTEST BST instruction on a blank ISP- or in-circuit reconfigurability (ICR)-capable device?
- Solutions/Find Answers…
- Learn About Altera's IEEE 1532 Solution
- Learn the Secrets of MAX II
- Boundary-Scan Tools Vendor Support
- IEEE 1532 Programming
- Jam Standard Test and Programming Language (STAPL)
- Jam STAPL Vendor Support
- In-Circuit Testers
- In-Circuit Testers Vendor Support