JTAG Configuration

The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Serial Vector File (SVF) is supported in Altera^® devices using third party programming tools. Altera devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an Altera download cable or an intelligent host, such as a microprocessor.

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Method

• Using a download cable for in-system programmability (ISP) and prototyping

Embedded Solutions

• JRunner (PDF)
  • Portable software driver used to configure an FPGA via a JTAG interface
  • Works on a PC or embedded processors
  • ByteBlaster^TM II or ByteBlasterMV^TM download cable can be used
  • Source code (ZIP) available for porting to an embedded system or other platform
• Jam STAPL player (PDF)
  • Offers in-system programming (ISP) via JTAG interface
  • Works on a PC or embedded processors
  • ByteBlaster II or ByteBlasterMV download cable can be used
  • Source code available for porting to an embedded system or other platform

Related Literature

• IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix IV Devices (PDF)
• IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices (PDF)
• IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II and Stratix II GX Devices (PDF)
• IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices (PDF)
• IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices (PDF)
• IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices (PDF)
• JTAG Boundary-Scan Testing for Arria II Devices (PDF)
• AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices (PDF)