JTAG Configuration
The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Serial Vector File (SVF) is supported in Intel® FPGA devices using third party programming tools. Intel FPGA devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an Intel FPGA download cable or an intelligent host, such as a microprocessor.
Configuration Method
- Intel® FPGA Download Cables
- Using download cable to download configuration data or to program data during prototyping into the system during production.
- JRunner
- Portable software driver used to configure an FPGA via a JTAG interface.
- Works on a PC or embedded processors.
- ByteBlasterTM II or ByteBlasterMVTM download cable can be used.
- Source code available for porting to an embedded system or other platform.
- Jam STAPL player
- Offers in-system programming (ISP) via JTAG interface.
- Works on a PC or embedded processors.
- ByteBlaster II or ByteBlasterMV download cable can be used.
Documentation
- Stratix® IV Device Handbook, Volume 1, Chapter 12: JTAG Boundary-Scan Testing
- IEEE 1149.1 (JTAG) Boundary-scan testing in Stratix® III Devices
- IEEE 1149.1 (JTAG) Boundary-scan testing in Stratix® II and Stratix II GX Devices
- IEEE 1149.1 (JTAG) Boundary-scan testing for Cyclone® III Devices
- IEEE 1149.1 (JTAG) Boundary-scan testing for Cyclone® II Devices
- IEEE 1149.1 (JTAG) Boundary-scan testing for Arria GX Devices
- JTAG Boundary-scan testing for Arria II Devices
- AN 39: IEEE 1149.1 (JTAG) Boundary-scan testing in Intel FPGA Devices