To meet the continuously increasing demand for faster configuration times, Altera® devices offer fast passive parallel (FPP) configuration with different data bus widths: 8 bit data width (FPP x8), 16 bit data width (FPP x16), and 32 bit data width (FPP x32). The FPP x16 and FPP x32 schemes are supported only in Stratix® V devices.
For more information, refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.
- Use a processor as an external host
- Use a MAX® series CPLD as an external host
Configuring the MicroBlasterTM FPP Software Driver white paper (PDF)
- Portable software driver used to configure an FPGA via an FPP interface
- Source code (ZIP) available for porting to an embedded system or other platform
AN 386: Using the Parallel Flash Loader with the Quartus® II Software (PDF)
- Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA
MAX Series Configuration Controller Using Flash Memory white paper (PDF)
- Using a MAX or MAX II CPLD as a configuration controller to configure Altera FPGAs from flash memory
- Source code (ZIP) in Verilog and VHDL