EMIF Calibration Checklist

This guideline is to help you troubleshoot in the calibration failure for external memory interfaces design using UniPHY on Altera devices. This serves as a first step debug on the design prior to seeking technical assistance from factory application team. You can use this guideline to help you identify possible causes of calibration failure. While this guideline does not cover every possible case, it does identify a majority of conditions that could lead to calibration failure.

FAQs and checklist are provided to assist you in troubleshooting the issue.

FAQ

What is the basic UniPHY IP related parameters that will impact calibration?

Q. Will the calibration fail if board settings not enter correctly?
A. Yes. Calibration is board specific and will need the board setting to be entered correctly. Run board trace simulation to determine the board traces delays and entered it correctly.
Choose the Setup and Hold Derating factor as what is specified on the memory vendor datasheet.

Q. Will the address and command skew affect calibration?
A. Yes. Calibration will failing if you have the incorrect addr/cmd skew. Calibration will fail at the first read stage.

Q. How important is the timing parameter in calibration issue?
A. Incorrect timing parameters such as CAS latency, address and command to write data alignment may cause calibration to fail. It will fail during write latency calibration stage for UniPHY.
Memory parameter will need to follow the specific operating speed of the design, not following the memory speed.

Q. Should I regenerate the IP if I’ve just upgraded the Quartus® Prime or Quartus II version? (e.g., from 13.1 to 14.0?)
A. Yes, you should always regenerate the IP when moving from one version of Quartus Prime or Quartus II software to another. This is to ensure the project has the correct version of UniPHY and controller. You will have the latest UniPHY but you still have the old controller if the IP is not regenerated.

Q. Will setup & hold time imbalance cause calibration failure?
A. No. But you can change the phase setting on the GUI to make the clock skew more balance.

Q. Will implementing over constraints cause calibration failure?
A. It could be. Please ensure that you fully understand the impact of the specific over constraints to the EMIF functionality before implementing the constraint on the design.

Q. How do I check for the release clears before tri-states setting?
A. Release clear before tri-states setting will affect calibration failure for non V series devices. To check for release clear before tri-state setting: Assembler>Settings>release clears before tri-states
If this is not at ‘off’ stage, please add the below assignment in the QSF file:
“set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES OFF” Both the setting and default value should be ‘off’

Q. Does port definition important in VHDL?
A. Yes. Port definition and assignment are important in VHDL as wrong definition will cause the Quartus Prime or Quartus II software to be unable to connect the ports properly. And this might cause the design unable to come out of calibration.

What are the basic board designs that will impact calibration?

Q. Will board layout have an impact on calibration?
A. Yes. Board layout which has been design badly will cause calibration failure. Follow the board layout guideline when designing the board.

Q. How do I check if it is noise/jitter from other part of the board cause the calibration failure?
A. Noise or jitter from other interface or operation can corrupt the interface signal. Always debug in quiet condition or switching off all the other operation on the board and run the standalone design which has the problem.

Q. Why does the CK signal needs to be longer than DQS signals on the PCB?
A. The CK needs to be longer than DQS because only the DQS signals can be adjusted (delayed) during calibration.

Q. Can I have the mem_reset_n signal terminated to Vtt on the board?
A. No. Altera recommends not terminate mem_reset_n at all. The Micron spec does not mention any pull-ups or pull-downs either. Please confirm the board termination is align with JEDEC specifications.

Q. Can I use 2 different memory devices on the same board?
A. If you are using 2 different memory devices (interchangeably) in the same board, use worst case value from both of the memory interfaces in the GUI parameters for memory device and PCB environment.

Q. Can I remove the Vtt termination on the Addr/Cmd signals?
A. No. Please make sure the Vtt is terminated and de-coupled properly.

What are the known issues that caused calibration failure?

Q. Will this be related to the fPLL issue?
A. It might be. Please ensure that you have the latest silicon version which has the fPLL fix. Else, please check the PLL phasdone and lock signal. If that is stuck low, it is related to the PLL global issue.

Q. Will this be related to the HPS PLL lock issue?
A. It might be. This issue can cause failure in any stage of calibration process. This issue has been fixed in Quartus II version 13.1 and 14.0 via patches.

What are the known issues which has been fix in the latest software version?

Q. DQS logic issue on V series
This issue has not caused any calibration failure before. To confirm, you have to route out the dll_delayctrlout signal in Signal Tap and observed the transition when Read data from Read FIFO is corrupted. This issue is fixed in the Quartus® II version 13.0SP1 DP5.

Q. HMC read/write error
A. The HMC-IOREG read failure issue does not cause calibration failure. This issue is fix in the Quartus® II version 13.0SP1 DP5 (Arria V and Cyclone FPGA) and 13.1 ( Arria V SoC and Cyclone V SoC) and onwards.

Q. DM calibration issue
A. Older calibration sequence for the DM pin is not optimum and this may cause calibration failure. Check the calibration report for the data valid window for the DM pins. If the data valid window is zero, then it is related to this issue. Update to the Quartus Prime or Quartus II software v13.0 or higher  for the fix for this issue.

Q. HPS SDRAM calibration failure in Quartus II version 13.1.1 and 13.1.2
A. It might be. Customer using Quartus II version 13.1.1 and 13.1.2 will encounter SDRAM calibration failure in Stage1, Sub-stage 1. This issue is fixed in Quartus II version 13.1.3.

Q.High current drawn on Vref pins for HPS DDR3
A. It might be. This issue can cause failure in calibration process when customer is using Quartus II version 13.0 or 13.0SP1. This issue has been fixed in the Quartus Prime or Quartus II software version 13.1 and higher.

What are the additional information should I submitted in the Service Request for further assistance from the factory application team?

  1. Basic design/project information with archive project attached.
  2. List out the failing condition.
  3. Prepare a SignalTap2 which has the required signals.
    • Trigger calibration fail signal for the design that fails calibration.
    • Trigger the status fail signal for the design that fail read/write test.
  4. Use the debug toolkit to check on the margin/window. Generate the debug report on debug toolkit.
  5. List out any changes done to the default UniPHY constraints in the Service Request.
  6. Try to reproduce the issue using Altera Exmpale design

Check list for troubleshooting calibration failure

    Yes No
1. Is the design able to close timing in the Quartus Prime or Quartus II software? DDR timing clean.
2. The board layout is following the board layout guideline on the EMI handbook.
3. The pin placement in the design is following the pin guidelines.
4. The device and interface can support the configuration as stated in spec estimator.
5. The memory parameter in the Quartus Prime or Quartus II software accurately represents the operation configuration and condition.
6. The OCT and ODT settings are correct.
7. For single rank DDR3, set the GUI setting to "Dynamic ODT Off"
8. The correct memory timing parameter for the interface that you are using is input into the Quartus Prime or Quartus II software.
9. Do you have the accurate board skews are input into the Quartus Prime or Quartus II software wizard?
10. Does the problem exist in the previous version of Quartus Prime or Quartus II software?
11. Regenerate the IP when upgrading the Quartus Prime or Quartus II software version.
12. Did you try using RTL sequencer if Nios II sequencer failed for RLDRAM II or QDR II interface?
13. Have you check the voltage supply to make sure all the voltage levels are correct? List of voltage are:
  • VCCIO
  • VCCINT
  • VCCD_PLL
  • VCC
  • VTT
  • VREF
14. Are the Addr/Cmd signal terminations done correctly?
15. Are the Addr/Cmd signal center aligned to the memory clock on the memory side?
16. Do you have a floating DM pins?
17. Are the OCT pin connections and OCT rules are followed on your board?.
18. Are the Rup and Rdn or Rzq pin connected properly on both FPGA and interface side on your board?
19. Did you modify any UniPHY default constraints?
20. Does the problem exist on just this PCB or a number of PCBs?
21. Does the design pass at different operating temperature?
22. Are the skew between signals within each DQ group 50ps or less?
23. Check on the warning message on the Quartus Prime or Quartus II report.
24. Does the design pass when running at a lower operating frequency?
25. Does the design pass while using memory with faster memory part?
26. Run the standalone interface that has problem and power down all the other interfaces. Does it pass?
27. Generate an example design with the same device and memory settings and apply the same pin assignment. Does it pass?