Devices Support Center

FPGAs	Configuration and Programming
Intel® Agilex™ Intel® Stratix® 10 Stratix V Stratix IV Stratix III Stratix II and Stratix II GX Stratix and Stratix GX Intel® Arria® 10 Arria V Arria II Arria GX Intel® Cyclone® 10 GX Intel® Cyclone® 10 LP Cyclone^® V Cyclone IV Cyclone III Cyclone II Cyclone Intel® MAX® 10	Programming Center Programming Tools Configuration Center Configuration via Protocol (CvP) FPGA Configuration Schemes
CPLDs	Power Management
MAX^® V MAX II MAX 3000A MAX 7000	Power Management Early Power Estimators EPE Debug Checklist SmartVID Debug Checklist
ASICs	I/O
HardCopy^® IV HardCopy III HardCopy II HardCopy Stratix HardCopy APEX™	I/O Features I/O Specifications Hot Socketing
Downloads	PLL and Clock Management
Device Pin-Outs Boundary-Scan Description Language (BSDL) and Boundary-Scan Test (BST) SPICE Models IBIS Models Schematic Review Worksheets Layout Review Worksheets Cadence Printed Circuit Board (PCB) Libraries Mentor Graphics Printed Circuit Board (PCB) Libraries Gerber Files Literature	Overview Phase-Locked Loop (PLL) Basics Using PLLs in Software Jitter Information Clock Networks Glossary Possible Causes for PLL Loss of Lock PLL Loss of Lock Checklist
Packaging and Board Design	Failure Analysis
Package and Thermal Resistance Package Drawing Search Layouts and Sockets Manufacturing	Failure Analysis Overview Failure Analysis Capabilities
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