The amount of logic used in the device and output switching requirements define decoupling requirements. Additional decoupling capacitance is needed as the number of I/O pins and the capacitive load on the pins increases. Designers should add as many 0.2 µF power-supply decoupling capacitors as possible to the V_{CCINT}, V_{CCIO}, and ground pins/planes. Ideally, these small capacitors should be located as close as possible to the device. Designers can decouple each V_{CCINT} or V_{CCIO} and ground pin pair with a 0.2-µF capacitor. If a design uses high-density packages such as ball grid array (BGA) packages, it may be difficult to use one decoupling capacitor per V_{CCINT} / V_{CCIO} and ground pin pair. In such cases, designers make every effort to use as many decoupling capacitors as allowed by the layout. Decoupling capacitors should have a good frequency response, such as monolithic-ceramic capacitors.

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Capacitor Choice & Placement

Proper placement and location are very important for high-frequency capacitors (0.001 to 0.1 µF low inductance ceramic chip). Designers should minimize trace lengths when possible to reduce the inductance in the path from capacitor terminals to the device power pins. This includes paths that go through a solid ground or power plane (V_{CCINT} or V_{CCIO}) where the inductance of one inch of solid copper plane is about 1 nH. Bypass capacitor vias should route directly to ground, V_{CCINT}, or V_{CCIO} planes. Other capacitor types (47 to 100 µF medium-frequency and 470 to 3,300 µF low-frequency capacitors) are referred to as “bulk” capacitance and can be mounted anywhere on the board. Designers should, however, locate bulk capacitance as close to the device as possible. Place V_{CCINT} or V_{CCIO} high-frequency bypass capacitors within one centimeter of the associated V_{CCINT} or V_{CCIO} pin on the PCB. V_{CCINT} or V_{CCIO} medium-frequency bypass capacitors should be placed within 3 cm of V_{CCINT} or V_{CCIO} pins.

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V_{CCINT} Bypass Capacitance

In the case of Stratix^{®} II, individual logic array structures within different architectural features conduct very small currents (picoamps or less) for very short durations (< 50 ps). Although these currents are small, when added up across the entire device they can add up to several amperes of current. Considering that these minute current transitions can occur hundreds of millions of times per second, along with the existence of millions of individual switches carrying out these transitions, bypass capacitor calculation is based on an average energy storage requirement. High-frequency capacitor values can be approximated with:

logic array power = equivalent switched logic array capacitance × V_{CCINT}^{2} × clock frequency

or

equivalent switched logic array capacitance = (logic array power) / (V_{CCINT}^{2} × clock frequency)

The equivalent switched logic array capacitance is the equivalent switched capacitance of the entire Stratix II logic array powered by V_{CCINT}. In order to reduce power noise, the V_{CCINT} power supply bypass capacitor must be significantly larger than the equivalent switched logic array capacitance. High-frequency bypass capacitors should be 25 to 100 times larger than the equivalent switched logic array capacitance. A factor of 50 will result in a 2 percent variation of V_{CCINT}.

High-frequency bypass capacitance = <*25 to 100*> × equivalent switched logic array capacitance

Every V_{CCINT} and ground pin pair should have a high-frequency bypass capacitor. To determine the optimum size of each high-frequency bypass capacitor, divide the total high-frequency bypass capacitance by the number of V_{CCINT} pins on the device, and round up to the next commonly available value. Therefore, the minimum size of each high-frequency V_{CCINT} capacitor is: